Abstract: A method for treating wastewater comprising subjecting a sulfate containing wastewater to Fe(III) iron dosing in an anaerobic bioreactor containing one or more of an iron reducing bacteria and one or more of a sulfate reducing bacteria, and one or more of a fermentative bacteria, and adjusting a dosage of the Fe(III) iron in the anaerobic bioreactor to achieve a Fe/Sulfate molar ratio that is equal to or greater than 0.50, and removing an effluent from the anaerobic bioreactor that is a treated wastewater. A wastewater treatment system is provided having a wastewater reservoir, a ferric iron solution reservoir, an anaerobic bioreactor, and an effluent reservoir.

Abstract: A method includes detecting a location of a particle on a bottom surface of an electrostatic chuck; moving a platform to a position under the bottom surface of the electrostatic chuck and right under the particle; and rotating the platform about a center of the platform to remove the particle from the bottom surface of the electrostatic chuck.

Abstract: This disclosure provides systems, methods, and apparatuses for wireless communication that can be used to reduce the peak-to-average power ratio (PAPR) of data transmissions by increasing the degree of randomness with which data is scrambled for transmission over a wireless medium. In some implementations, a transmitting device may determine a scrambler seed value that includes at least 11 bits, where at least one of the 7 least significant bits (LSBs) of the scrambler seed value has a non-zero value. The transmitting device may generate a scrambling sequence based on the scrambler seed value and a polynomial, may construct a physical layer convergence protocol (PLCP) protocol data unit (PPDU) that includes a multi-user (MU) request-to-send (RTS) frame and the scrambler seed value, may scramble one or more portions of the PPDU based on the scrambling sequence; and may transmit the PPDU over a wireless medium.

Abstract: A power supply system providing a power conversion function for a system circuit includes first, second and third convertor circuits respectively including plural switches and first, second and third inductors. The first and second convertor circuits are coupled to first and second power supplies respectively through first and second ports of the system circuit. A third power supply is coupled to a battery module and an internal load circuit. The plural switches are configured to correspondingly switch the first to third inductors to perform power conversion between the first to third power supplies and an internal power bus of the system circuit. The voltage of the internal power bus is configured to be higher than any voltage of the first to third power supplies, such that a current of the internal power bus is lower than a third current of the third power supply.

Abstract: A neutron capture therapy system is provided, including a neutron generating device and a beam shaping assembly. The neutron capture therapy system further includes a concrete wall forming a space for accommodating the neutron generating device and the beam shaping assembly and shielding radiations generated by the neutron generating device and the beam shaping assembly. A support module is disposed in the concrete wall, the support module is capable of supporting the beam shaping assembly and is used to adjust the position of the beam shaping assembly, and the support module includes concrete and a reinforcing portion at least partially disposed in the concrete. The neutron capture therapy system designs a locally adjustable support for the beam shaping assembly, so that the beam shaping assembly can meet the precision requirement, improve the beam quality, and meet an assembly tolerance of the target.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: A 10 G rate OLT terminal transceiver integrated chip based on XGPON and DFB laser includes: a burst mode receiver RX, a continuous mode transmitter TX and a digital control unit DIGIITAL. The burst mode receiver RX amplifies an optical signal from each ONU client into an electrical signal through a burst TIA, processes double-detection for amplitude and frequency of the electrical signal, outputs the signal whose amplitude and waveform pulse width meet the threshold requirements to the host, and uses a fast recovery module to control the timing to meet the XGPON protocol. The continuous mode transmitter TX receives the electrical signal attenuated by the PCB, and selects the bypass BYPASS path or the clock data recovery CDR path according to the degree of attenuation. The digital control unit DIGIITAL is used to provide control signals for the burst mode receiver RX and the continuous mode transmitter TX.

Abstract: An electronic device is provided. The electronic device includes a first panel. The first panel includes a first substrate, a second substrate, a liquid crystal layer, a first transparent electrode, a second transparent electrode, and a first signal line. The second substrate is opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The first transparent electrode is disposed between the first substrate and the liquid crystal layer. The second transparent electrode is disposed between the second substrate and the liquid crystal layer. The first signal line is electrically connected to the first transparent electrode and extending along a first direction. The impedance of the first signal line is less than the impedance of the first transparent electrode.

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Abstract: The present application provides an antibody, such as a monoclonal antibody (mAb), or an antigen binding fragment thereof, that specifically recognizes PD-L1. Also provided are pharmaceutical compositions, or methods of making and using the antibody or antigen binding fragment thereof.

Abstract: A full-automatic detection apparatus and system for important zoonotic pathogen, and a control method therefor. The full-automatic detection apparatus for important zoonotic pathogen includes: a base capable of moving; an air collection device, configured to collect a to-be-detected sample in air along with the movement of the base; a nucleic acid detection and analysis device, configured to detect the to-be-detected sample collected by the air collection device to determine whether an infectious pathogen exists in the to-be-detected sample; an intelligent mobile device, configured to plan and control a moving path of the base; and a control device, configured to control the intelligent mobile device to plan and control the moving path of the base and to control a sampling period of the air collection device according to a control instruction of the terminal, and transmit a detection result from the nucleic acid detection and analysis device to the terminal.

Abstract: A memory structure includes: a substrate including a memory array region and a peripheral circuit region; a plurality of bit line structures disposed in the memory array region of the substrate; a dummy bit line structure disposed on the substrate, wherein the dummy bit line structure is disposed in the memory array region and immediately adjacent to the peripheral circuit region; a plurality of contacts disposed between the bit line structures and in the memory array region; a dielectric layer disposed on the substrate and in the peripheral circuit region; and a protective structure disposed in the memory array region and immediately adjacent to the peripheral circuit region, wherein the protective structure includes the dummy bit line structure and a top surface of the protective structure is higher than top surfaces of the bit line structures.

Abstract: A carrier device and a placement machine, where the carrier device includes a body and a positioner. A positioning sucker mechanism is disposed on the body, and a sliding sucker mechanism is slidably disposed on the body, where the sliding sucker mechanism includes a sucker group, a positioning block connected to one end of the sucker group, and a first suction piece provided on the positioning block. The positioner is arranged on one side of the body and adjacent to the positioning block, and includes a driver and a clamping assembly connected to the driver, where the clamping assembly is provided with a second suction piece mutually attracted to the first suction piece.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.

Abstract: An integrated multi-port solenoid valve, comprising: at least two sub-solenoid valves (20), each sub-solenoid valve (20) comprising at least two connection ports; and at least one first joint (30), each first joint (30) comprising at least two connection joints, wherein at least one first connection port in the at least two connection ports is used for connection to other sub-solenoid valves (20), each first joint (30) is used for connecting any two sub-solenoid valves (20), and each connector joint is connected to the first connection port. The present integrated multi-port solenoid valve integrates multiple sub-solenoid valves, and any connection ports of each sub-solenoid valve is communicated with each other to meet control requirements of a variety of working conditions. The integrated multi-port solenoid valve has lightweight design, few components, a light weight, and low cost of use. Also provided are a vehicle thermal management system and a vehicle.