Patents by Inventor Linda T. Romano

Linda T. Romano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10312404
    Abstract: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 4, 2019
    Assignee: LUMILEDS LLC
    Inventors: Sungsoo Yi, Nathan F. Gardner, Michael R. Krames, Linda T. Romano
  • Publication number: 20180175236
    Abstract: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: Sungsoo Yi, Nathan F. Gardner, Michael R. Krames, Linda T. Romano
  • Patent number: 9911896
    Abstract: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: March 6, 2018
    Assignees: Koninklijke Phillips N.V., Lumileds LLC
    Inventors: Sungsoo Yi, Nathan F. Gardner, Michael R. Krames, Linda T. Romano
  • Publication number: 20130015552
    Abstract: Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion.
    Type: Application
    Filed: July 12, 2011
    Publication date: January 17, 2013
    Applicant: EPOWERSOFT, INC.
    Inventors: Isik C. Kizilyalli, David P. Bour, Richard J. Brown, Andrew P. Edwards, Hui Nie, Linda T. Romano
  • Publication number: 20120309172
    Abstract: A method of reusing a III-nitride growth substrate according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor structure on a III-nitride substrate. The III-nitride semiconductor structure includes a sacrificial layer and an additional layer grown over the sacrificial layer. The sacrificial layer is implanted with at least one implant species. The III-nitride substrate is separated from the additional layer at the implanted sacrificial layer. In some embodiments the III-nitride substrate is GaN and the sacrificial layer is GaN, an aluminum-containing III-nitride layer, or an indium-containing III-nitride layer. In some embodiments, the III-nitride substrate is separated from the additional layer by etching the implanted sacrificial layer.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: EPOWERSOFT, INC.
    Inventors: Linda T. Romano, David P. Bour, Richard J. Brown, Andrew P. Edwards, Isik C. Kizilyalli, Hui Nie, Thomas R. Prunty
  • Patent number: 8293624
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 23, 2012
    Assignee: Nanosys, Inc.
    Inventors: Linda T. Romano, Jian Chen
  • Publication number: 20120264248
    Abstract: A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Linda T. ROMANO, Parijat Pramil DEB, Andrew Y. Kim, John F. KAEDING
  • Publication number: 20120248577
    Abstract: A method according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor layer from a gas containing gallium, a gas containing nitrogen, and a gas containing indium. The concentration of indium in the III-nitride semiconductor structure is greater than zero and less than 1020 cm?3. A structure according to embodiments of the invention includes a super lattice of alternating first and second III-nitride layers. The first layers are more highly doped than the second layers. The average dopant concentration in the super lattice is less than 1020 cm?3.
    Type: Application
    Filed: April 4, 2011
    Publication date: October 4, 2012
    Applicant: EPOWERSOFT INC.
    Inventors: Linda T. Romano, David P. Bour, Isik C. Kizilyalli, Hui Nie, Thomas R. Prunty
  • Publication number: 20110312163
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 22, 2011
    Applicant: NANOSYS, INC.
    Inventors: Linda T. Romano, Jian Chen
  • Patent number: 8030186
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 4, 2011
    Assignee: Nanosys, Inc.
    Inventors: Linda T. Romano, Jian Chen
  • Publication number: 20110177638
    Abstract: A semiconductor structure is grown on a top surface of a growth substrate. The semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. A curvature control layer is disposed in direct contact with the growth substrate. The growth substrate has a thermal expansion coefficient less than a thermal expansion coefficient of GaN and the curvature control layer has a thermal expansion coefficient greater than the thermal expansion coefficient of GaN.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 21, 2011
    Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS LUMILEDS LIGHTING COMPANY, LLC
    Inventors: Linda T. ROMANO, Byung-kwon HAN, Michael D. CRAVEN
  • Patent number: 7951422
    Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: May 31, 2011
    Assignee: Nanosys, Inc.
    Inventors: Yaoling Pan, Xiangfeng Duan, Robert S. Dubrow, Jay Goldman, Shahriar Mostarshed, Chunming Niu, Linda T. Romano, David P. Stumbo, Alice Fischer-Colbrie, Vijendra Sahi, Virginia Robbins
  • Patent number: 7951693
    Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: May 31, 2011
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventors: Patrick N. Grillot, Nathan F. Gardner, Werner K. Goetz, Linda T. Romano
  • Patent number: 7932511
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 26, 2011
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence Bock, David Stumbo, J. Wallace Parce, Jay L. Goldman
  • Publication number: 20110057213
    Abstract: A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer.
    Type: Application
    Filed: September 8, 2009
    Publication date: March 10, 2011
    Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS LUMILEDS LIGHTING COMPANY, LLC
    Inventors: Linda T. ROMANO, Parijat Pramil DEB, Andrew Y. KIM, John F. KAEDING
  • Publication number: 20110045660
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Application
    Filed: November 5, 2010
    Publication date: February 24, 2011
    Applicant: NANOSYS, INC.
    Inventors: Linda T. Romano, Jian Chen
  • Patent number: 7871870
    Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: January 18, 2011
    Assignee: Nanosys, Inc.
    Inventors: Shahriar Mostarshed, Jian Chen, Francisco A. Leon, Yaoling Pan, Linda T. Romano
  • Publication number: 20100323500
    Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.
    Type: Application
    Filed: August 11, 2010
    Publication date: December 23, 2010
    Applicant: NANOSYS, INC.
    Inventors: Mihai Buretea, Jian Chen, Calvin Chow, Chunming Niu, Yaoling Pan, J. Wallace Parce, Linda T. Romano, David Stumbo
  • Patent number: 7851841
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: December 14, 2010
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen A. Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence Bock, David P. Stumbo, J. Wallace Parce, Jay L. Goldman
  • Publication number: 20100285972
    Abstract: This invention provides novel nanofiber enhanced surface area substrates and structures comprising such substrates, as well as methods and uses for such substrates.
    Type: Application
    Filed: October 17, 2007
    Publication date: November 11, 2010
    Applicant: Nanosys, Inc.
    Inventors: Roberto Dubrow, Robert Hugh Daniels, J. Wallace Parce, Matthew Murphy, Jim Hamilton, Erik Scher, Dave Stumbo, Chunming Niu, Linda T. Romano, Jay Goldman, Vijendra Sahi, Jeffery A. Whiteford