Patents by Inventor Lindsey H. Hall
Lindsey H. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9252050Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: GrantFiled: September 11, 2012Date of Patent: February 2, 2016Assignees: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
-
Patent number: 9230857Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: GrantFiled: October 23, 2014Date of Patent: January 5, 2016Assignees: International Business Machines Corporation, St. Microelectronics Inc.Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
-
Publication number: 20150044869Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: ApplicationFiled: October 23, 2014Publication date: February 12, 2015Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Fillippos Papadatos, Yiyi Wang
-
Publication number: 20140073131Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: ApplicationFiled: September 11, 2012Publication date: March 13, 2014Applicants: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
-
Patent number: 8053252Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: GrantFiled: July 14, 2009Date of Patent: November 8, 2011Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
-
Patent number: 7799582Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: GrantFiled: July 14, 2009Date of Patent: September 21, 2010Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
-
Patent number: 7723199Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: GrantFiled: January 31, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
-
Publication number: 20090275148Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: ApplicationFiled: July 14, 2009Publication date: November 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. UDAYAKUMAR, Lindsey H. HALL, Francis G. CELII
-
Publication number: 20090275147Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: ApplicationFiled: July 14, 2009Publication date: November 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. UDAYAKUMAR, Lindsey H. HALL, Francis G. CELII, Scott R. SUMMERFELT
-
Patent number: 7572698Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: GrantFiled: May 30, 2006Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
-
Patent number: 7517779Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.Type: GrantFiled: July 2, 2007Date of Patent: April 14, 2009Assignee: Texas Instruments IncorporatedInventor: Lindsey H. Hall
-
Patent number: 7422967Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).Type: GrantFiled: May 12, 2005Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Juanita DeLoach, Lindsey H. Hall, Lance S. Robertson, Jiong-Ping Lu, Donald S. Miles
-
Patent number: 7371691Abstract: The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.Type: GrantFiled: July 29, 2004Date of Patent: May 13, 2008Assignee: Texas Instruments IncorporatedInventors: Lindsey H. Hall, Trace Q. Hurd, Deborah J. Riley
-
Publication number: 20070298521Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: ApplicationFiled: January 31, 2007Publication date: December 27, 2007Applicant: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
-
Publication number: 20070281422Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.Type: ApplicationFiled: May 30, 2006Publication date: December 6, 2007Inventors: Kezhakkedath R. Udayakumar, Lindsey H. Hall, Francis G. Celii, Scott R. Summerfelt
-
Patent number: 7253049Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.Type: GrantFiled: December 20, 2004Date of Patent: August 7, 2007Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Shaofeng Yu, Haowen Bu, Lindsey H. Hall, Mark R. Visokay
-
Patent number: 7252773Abstract: One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that includes fluorine-containing radicals. The plasma removes a small layer from the capacitors, including their sidewalls, and thereby removes surface contaminants. The method is effective even when the capacitors include hard-to-etch dielectric materials, such as tantalum and hafnium oxides. In a preferred embodiment, the plasma clean is combined with a solvent clean.Type: GrantFiled: October 11, 2002Date of Patent: August 7, 2007Assignee: Texas Instruments IncorporatedInventor: Lindsey H. Hall
-
Patent number: 7228865Abstract: An embodiment of the invention is a method of cleaning a material stack 2 that has a hard mask top layer 8. The method involves cleaning the material stack 2 with a fluorine-based plasma etch. The method further involves rinsing the material stack 2 with a wet clean process.Type: GrantFiled: May 28, 2003Date of Patent: June 12, 2007Assignee: Texas Instruments IncorporatedInventors: Lindsey H. Hall, Scott R. Summerfelt
-
Patent number: 7220600Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.Type: GrantFiled: December 17, 2004Date of Patent: May 22, 2007Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Lindsey H. Hall, Kezhakkedath R. Udayakumar, Theodore S. Moise, IV
-
Publication number: 20040237998Abstract: An embodiment of the invention is a method of cleaning a material stack 2that has a hard mask top layer 8. The method involves cleaning the material stack 2with a fluorine-based plasma etch. The method further involves rinsing the material stack 2with a wet clean process.Type: ApplicationFiled: May 28, 2003Publication date: December 2, 2004Inventors: Lindsey H. Hall, Scott R. Summerfelt