Abstract: A heat dissipation device includes a first heat dissipation member, a second heat dissipation member, and a heat conduction member. The heat conduction member can be U-shaped. The first heat dissipation member and the second heat dissipation member are located on two ends of the heat conduction member. The two ends of the heat conduction member are substantially parallel to each other. One end of the heat conduction member is engaged with a heating element and conducts heat to the first heat dissipation member and the second heat dissipation member. A heat dissipation system with the heat dissipation device is also provided.

Abstract: A system and method for speech-to-singing synthesis is provided. The method includes deriving characteristics of a singing voice for a first individual and modifying vocal characteristics of a voice for a second individual in response to the characteristics of the singing voice of the first individual to generate a synthesized singing voice for the second individual.

Abstract: A harmony synthesizer is described for harmonizing vocal signals. The harmony synthesizer performing a method comprising receiving an input vocal signal; identifying a pitch trace of the vocal signal; aligning the harmonization interval vector(s) to the pitch trace of the vocal input signal to form an aligned harmonization pitch trace; and synthesizing harmonization vocals according to the aligned harmonization pitch trace.

Abstract: Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.

Abstract: The invention facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.

Abstract: Methods and apparatus to quiesce and/or de-quiesce links (such as point-to-point link) in a multi-processor system are described. In one embodiment, one or more bits are modified to indicate the status of quiesce/dequiesce processes.

Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Abstract: In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request in parallel with obtaining data of the speculatively provided read request, and providing the data of the speculatively provided read request to the processor if the read request is coherent. In this way, data may be used by a processor with a reduced latency. Other embodiments are described and claimed.

Abstract: Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.

Abstract: A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.

Abstract: Arrangements facilitating ordered transactions, e.g., ordered writes, in a packet switch system having multiple switch elements.

Abstract: A system, apparatus, and method for a link layer protocol to utilize a main buffer and share the remaining link units according to a list buffer or FIFO. The system includes an efficient link layer to facilitate transmitting and receiving data and information. The list buffer is used to store the buffer indexes for all the link units for the respective virtual connections.

Abstract: The invention facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.

Abstract: The invention facilitates a messaging protocol in a multi-node system to resolve conflicts at a home node.

Abstract: A cache coherence protocol facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.

Abstract: A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.

Abstract: A system, apparatus, and method for a link layer protocol to utilize a main buffer and share the remaining link units according to a list buffer or FIFO.

Abstract: Arrangements facilitating ordered transactions, e.g., ordered writes, in a packet switch system having multiple switch elements.

Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Abstract: A method includes determining the node ID information of a second node device of a multi-node computer system. The method stores the node ID information of the second node device on a storage device located on a first node device of the multi-node computer system. The first node device is connected to the second node device and the second node device includes a storage device containing node ID information for a third node device connected to the second node device.