Abstract: A method and apparatus for enumeration of a multi-node computer system. A local bootstrap processor is selected using a local boot flag register from a group of local node processors. The local bootstrap processor is responsible for enumerating the local node elements. A global bootstrap processor is selected using a global boot flag register to be responsible for enumerating the components of the system. A server management device monitors enumeration progress.

Abstract: In a multi-node system, a method and apparatus to implement a locked-bus transaction is described. In one embodiment, a bus agent initiates a locked-bus transaction and a node controller defers the transaction so that it will be initiated again at a later time. The node controller then sends the locked bus request to one or more other node controllers in the system, which prevent bus transaction at their respective busses. Once the requesting node controller receives confirmation that the other nodes are locked, it can allow the locked-bus transaction to proceed from the bus agent.

Abstract: An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At_least_x_words_filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided.

Abstract: During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication to central processing units (CPUs). According to the invention, these IRQs are detected by a Secondary Interrupt Mapping (SIM) device which transports the signals according to a 2 bit bus protocol over a wired-"OR" bus structure to a Primary Interrupt Mapping (PIM) device located on the compatibility PCI bus. The PIM and SIM transport IRQs over the bus structure utilizing a timing sequence and 2-bit bus protocol. The PIM serves as the master device of the timing sequence and at appropriately designated sequence slots receives bus command signals from the SIM which map to particular interrupt signals that the PIM forwards to the interrupt controller on the compatibility PCI bus for transportation to the CPUs.

Abstract: An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- x.sub.-- words.sub.-- filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry.

Abstract: An electronic device (PPU 110) includes a data source (7201) supplying data and successive control signals indicative of valid-data, wherein transitions occur in the data during intervals between the signals indicative of valid-data, and a selector (7205) having a first input connected to the data source (7201), and a second input (7214), and an output. A circuit (7207) is connected to the output of the selector (7205) to receive data from the data source (7201) via the selector (7205). A source of a quieting signal (7220) is connected to the second input (7214), and the selector (7205) is responsive to the control signals (7206) to select the quieting signal (7220) during at least a portion of the interval between the signals indicative of valid data, and to select the data source in response to at least some of the successive control signals indicative of valid-data. Other devices, systems and methods are also disclosed.

Abstract: An electronic device (PPU 110) includes a data source (7201) supplying data and successive control signals indicative of valid-data, wherein transitions occur in the data during intervals between the signals indicative of valid-data, and a selector (7205) having a first input connected to the data source (7201), and a second input (7214), and an output. A circuit (7207) is connected to the output of the selector (7205) to receive data from the data source (7201) via the selector (7205). A source of a quieting signal (7220) is connected to the second input (7214), and the selector (7205) is responsive to the control signals (7206) to select the quieting signal (7220) during at least a portion of the interval between the signals indicative of valid data, and to select the data source in response to at least some of the successive control signals indicative of valid-data. Other devices, systems and methods are also disclosed.

Abstract: An electronic device (PPU 110) includes a data source (7201) supplying data and successive control signals indicative of valid-data, wherein transitions occur in the data during intervals between the signals indicative of valid-data, and a selector (7205) having a first input connected to the data source (7201), and a second input (7214), and an output. A circuit (7207) is connected to the output of the selector (7205) to receive data from the data source (7201) via the selector (7205). A source of a quieting signal (7220) is connected to the second input (7214), and the selector (7205) is responsive to the control signals (7206) to select the quieting signal (7220) during at least a portion of the interval between the signals indicative of valid data, and to select the data source in response to at least some of the successive control signals indicative of valid-data. Other devices, systems and methods are also described.