Patents by Inventor Ling-Chun Chou
Ling-Chun Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150108553Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: ApplicationFiled: December 26, 2014Publication date: April 23, 2015Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Patent number: 8951876Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: GrantFiled: June 20, 2012Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Patent number: 8841193Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.Type: GrantFiled: June 26, 2013Date of Patent: September 23, 2014Assignee: United Microelectronics Corp.Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
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Publication number: 20130341685Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Publication number: 20130292775Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: ApplicationFiled: July 8, 2013Publication date: November 7, 2013Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 8574978Abstract: A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.Type: GrantFiled: April 11, 2012Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Ling-Chun Chou, I-Chang Wang
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Publication number: 20130288446Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
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Publication number: 20130273706Abstract: A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Inventors: Ching-Wen Hung, Chih-Sen Huang, Ling-Chun Chou, I-Chang Wang
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Patent number: 8552503Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: GrantFiled: November 30, 2010Date of Patent: October 8, 2013Assignee: United Microelectronics Corp.Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 8502288Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.Type: GrantFiled: April 1, 2011Date of Patent: August 6, 2013Assignee: United Microelectronics Corp.Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
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Publication number: 20130183803Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.Type: ApplicationFiled: January 13, 2012Publication date: July 18, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventor: Ling-Chun Chou
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Patent number: 8486794Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.Type: GrantFiled: January 13, 2012Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventor: Ling-Chun Chou
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Publication number: 20130171789Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Inventors: Ling-Chun Chou, Shin-Chuan Huang, I-Chang Wang, Ching-Wen Hung, Buo-Chin Hsu, Yi-Han Ye
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Publication number: 20130089962Abstract: A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.Type: ApplicationFiled: October 11, 2011Publication date: April 11, 2013Inventors: Chung-Fu Chang, Shin-Chuan Huang, Yu-Hsiang Hung, Chia-Jong Liu, Pei-Yu Chou, Jyh-Shyang Jenq, Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung, Ted Ming-Lang Guo, Chun-Yuan Wu
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Publication number: 20120248511Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.Type: ApplicationFiled: April 1, 2011Publication date: October 4, 2012Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
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Patent number: 8273631Abstract: A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.Type: GrantFiled: December 14, 2009Date of Patent: September 25, 2012Assignee: United Microelectronics Corp.Inventors: I-Chang Wang, Ling-Chun Chou, Ming-Tsung Chen
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Publication number: 20120196421Abstract: An stress adjusting method includes the following steps. A substrate is provided. A first gate structure and a second gate structure adjacent to the first gate structure are formed on the substrate. Each of the first gate structure and the second gate structure includes a spacer. A source/drain implantation process is applied to the substrate by using the first gate structure with the spacer and the second gate structure with the spacer as a mask. After the source/drain implantation process, the spacers are thinned so as to increase a distance between the first gate structure and the second gate structure. A stress film is formed. A first annealing process is applied to the substrate having the stress film.Type: ApplicationFiled: February 1, 2011Publication date: August 2, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsung-Hung CHANG, Ling-Chun CHOU
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Publication number: 20120132996Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 8129235Abstract: A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer.Type: GrantFiled: March 15, 2007Date of Patent: March 6, 2012Assignee: United Microelectronics Corp.Inventors: Ling-Chun Chou, Ming-Tsung Chen, Po-Chao Tsao
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Publication number: 20110143511Abstract: A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.Type: ApplicationFiled: December 14, 2009Publication date: June 16, 2011Inventors: I-Chang Wang, Ling-Chun Chou, Ming-Tsung Chen