METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.
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1. Field of the Invention
The disclosure relates in general to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure, comprising a step for forming a compensation layer.
2. Description of the Related Art
With a trend of shrinking a line width of a semiconductor process, a size of a semiconductor structure, comprising for example a MOS transistor or a memory array, etc., has been scaled down. However, an accurate process is necessary for obtaining a fine critical size of a semiconductor process. Otherwise, a semiconductor device would have a low efficiency resulted from a process shift or a side effect in a manufacturing step.
SUMMARYA method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.
A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer and a cap layer are formed on a semiconductor substrate. The cap layer is on the patterned gate layer. A sidewall layer is formed on sidewalls of the patterned gate layer and the cap layer. The sidewall layer is removed. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. The cap layer is removed. The step for forming the compensation layer is between the step for removing the sidewall layer and the step for removing the cap layer.
The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
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The film layer 24 is patterned for forming a cap layer 28 as shown in
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In embodiments, semiconductor structures of different types are formed in the active region 16 and the active region 18, respectively. The lightly doped region 32A and the heavily doped region 48A in the active region 16 have a first type conductivity. The semiconductor substrate 12 in the active region 16 has a second type conductivity opposite to the first type conductivity. The lightly doped region 32B and the heavily doped region 48B in the active region 18 have the second type conductivity. The semiconductor substrate 12 in the active region 18 has the first type conductivity.
For example, a PMOS is formed in the active region 16, and a NMOS is formed in the active region 18, in which the first type conductivity is P type conductivity, and the second type conductivity is N type conductivity, and vice versa. In a case of a PMOS in the active region 16, the epitaxial layer 44 comprises SiGe. In a case of a NMOS in the active region 16, the epitaxial layer 44 comprises SiC. The lightly doped region 32A and the lightly doped region 32B are used as a LDD. The heavily doped region 48A and the heavily doped region 48B are used as a source/drain.
In some embodiments (not shown), the semiconductor structures in the active region 16 and the active region 18 may both have the epitaxial layers 44. In other embodiments (not shown), for example in a memory array, the STI 14 is omitted, and two adjacent gate structures use a common heavily doped region or epitaxial layer.
The patterned conductive layer 22′ of the patterned gate layer 26 may be used as a gate electrode or a dummy gate. In a case of the patterned conductive layer 22′ used as a gate electrode, a metal silicide may be formed on the patterned conductive layer 22′. The metal silicide may be an additional metal silicide formed after the cap layer 28 used as a mask layer is removed. In a case of the patterned conductive layer 22′ used as a dummy gate, a barrier layer (not shown) such as TiN is formed between the patterned dielectric layer 20′ and the patterned conductive layer 22′. In addition, the cap layer 28 is not removed before the patterned conductive layer 22′ (the dummy gate) for preventing a formation of a metal silicide on the patterned conductive layer 22′ (the dummy gate) that would make removing the patterned conductive layer 22′ (the dummy gate) difficult.
In embodiments, the compensation layer 34 can compensate losses of the substrate material generated in the removing steps. Therefore, a PN junction of a device can be controlled at a predetermined position. A short channel effect and a drain induced barrier lowering (DIBL) can be avoided. Forming the compensation layer 34 also makes a protruding portion 45 of the epitaxial layer 44 close to a channel. Therefore, a super shallow junction (USL) can be obtained. In addition, the efficiency of the device is improved.
Second EmbodimentThe second embodiment is different from the first embodiment in that the lightly doped regions in different active regions are respectively formed before and after the sidewall layer and the cap layer are removed.
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The sidewall layer 138, the material layer 140 and the cap layer 128 are removed by an etching step for forming the semiconductor structure as shown in
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The third embodiment is different from the first embodiment in that the lightly doped regions are formed after the sidewall layer and the cap layer are removed.
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The sidewall layer 238, the material layer 240 and the cap layer 228 are removed by an etching step for forming the semiconductor structure as shown in
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The fourth embodiment is different from the second embodiment in that the step for forming the compensation layer is between the step for removing the sidewall layer and the step for removing the cap layer.
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The sidewall layer 338 and the material layer 340 are removed by an etching step for forming the semiconductor structure as shown in
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Then, the cap layer 328 is removed by an etching step for forming the semiconductor structure as shown in
The lightly doped region 332B is then formed in the semiconductor substrate 312 in the active region 318. Since the lightly doped region 332B is formed after the sidewall layer 338 (
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The fifth embodiment is different from the third embodiment in that the step for forming the compensation layer is between the step for removing the sidewall layer and the step for removing the cap layer.
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The sidewall layer 438 and the material layer 440 are removed by an etching step for forming the semiconductor structure as shown in
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Then, the cap layer 428 is removed by an etching step for forming the semiconductor structure as shown in
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According to foregoing embodiments, the compensation layer can compensate losses of the substrate material generated in the removing steps. Therefore, a PN junction of a device can be controlled at a predetermined position and the efficiency of the device is improved. The compensation layer is not limited to the formation timing illustrated in the foregoing embodiments. In some cases, a plurality of compensation layers can be formed at different formation timings. In other words, for example, a plurality of compensation layers can be formed at an optional combination of formation timings illustrated in embodiments.
While the disclosure has been described by way of example and in terms of the exemplary preferred embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims
1. A method for manufacturing a semiconductor structure, comprising:
- forming a patterned gate layer on a semiconductor substrate;
- forming a compensation layer on the semiconductor substrate outside the patterned gate layer, wherein the compensation layer comprises silicon, SiGe, SiC, doped silicon;
- forming a trench in the compensation layer and the semiconductor substrate; and
- forming an epitaxial layer in the trench, wherein the step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.
2. The method for manufacturing the semiconductor structure according to claim 1, wherein the compensation layer is a silicon containing epitaxial material grown from the semiconductor substrate.
3. (canceled)
4. The method for manufacturing the semiconductor structure according to claim 1, wherein the patterned gate layer and the semiconductor substrate has an interface therebetween, in the step for forming the compensation layer, a top surface of the compensation layer is higher than or as high as the interface.
5. The method for manufacturing the semiconductor structure according to claim 1, further comprising forming a lightly doped region in the semiconductor substrate adjacent to the patterned gate layer, wherein the step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the lightly doped region.
6. The method for manufacturing the semiconductor structure according to claim 1, further comprising forming a lightly doped region in the semiconductor substrate adjacent to the patterned gate layer, wherein the step for forming the compensation layer is between the step for forming the lightly doped region and the step for forming the epitaxial layer.
7. The method for manufacturing the semiconductor structure according to claim 1, further comprising:
- forming a cap layer on the patterned gate layer;
- forming a sidewall layer on sidewalls of the patterned gate layer and the cap layer;
- removing the sidewall layer;
- removing the cap layer; and
- forming a lightly doped region in the semiconductor substrate adjacent to the patterned gate layer.
8. The method for manufacturing the semiconductor structure according to claim 7, wherein the step for forming the lightly doped region is after the step for removing the sidewall layer and the step for removing the cap layer.
9. The method for manufacturing the semiconductor structure according to claim 8, wherein the step for removing the sidewall layer and the step for removing the cap layer are performing simultaneously.
10. The method for manufacturing the semiconductor structure according to claim 7, wherein the step for forming the lightly doped region is before the step for removing the sidewall layer and the step for removing the cap layer.
11. The method for manufacturing the semiconductor structure according to claim 7, the step for removing the sidewall layer and the step for removing the cap layer are performing simultaneously.
12. The method for manufacturing the semiconductor structure according to claim 1, further comprising forming a spacer on a sidewall of the patterned gate layer, wherein the step for forming the compensation layer is between the step for forming the spacer and the step for forming the epitaxial layer.
13. A method for manufacturing a semiconductor structure, comprising:
- forming a patterned gate layer and a cap layer on a semiconductor substrate, wherein the cap layer is on the patterned gate layer;
- forming a sidewall layer on sidewalls of the patterned gate layer and the cap layer;
- removing the sidewall layer;
- forming a compensation layer on the semiconductor substrate outside the patterned gate layer, wherein the compensation layer comprises silicon, SiGe, SiC, doped silicon; and
- removing the cap layer, wherein the step for forming the compensation layer is between the step for removing the sidewall layer and the step for removing the cap layer.
14. The method for manufacturing the semiconductor structure according to claim 13, wherein the step for removing the cap layer is after the step for removing the sidewall layer.
15. The method for manufacturing the semiconductor structure according to claim 13, wherein the compensation layer is a silicon containing epitaxial material grown from the semiconductor substrate.
16. (canceled)
17. The method for manufacturing the semiconductor structure according to claim 13, wherein the patterned gate layer and the semiconductor substrate have an interface therebetween, in the step for forming the compensation layer, a top surface of the compensation layer is higher than or as high as the interface.
18. The method for manufacturing the semiconductor structure according to claim 13, further comprising forming a lightly doped region in the semiconductor substrate adjacent to the patterned gate layer, wherein the step for forming the lightly doped region is between the step for forming the patterned gate layer and the step for removing the sidewall layer.
19. The method for manufacturing the semiconductor structure according to claim 13, further comprising forming a lightly doped region in the semiconductor substrate adjacent to the patterned gate layer, wherein the step for forming the lightly doped region is after the step for removing the sidewall layer and the step for removing the cap layer.
20. The method for manufacturing the semiconductor structure according to claim 13, further comprising:
- forming a trench in the semiconductor substrate outside the patterned gate layer, wherein the step for forming the trench and the step for forming the sidewall layer are performed simultaneously; and
- forming an epitaxial layer in the trench.
Type: Application
Filed: Jan 13, 2012
Publication Date: Jul 18, 2013
Applicant: UNITED MICROELECTRONICS CORP. (HSINCHU)
Inventor: Ling-Chun Chou (Yunlin County)
Application Number: 13/349,602
International Classification: H01L 21/336 (20060101);