Abstract: Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.

Abstract: Memories, operation methods and memory systems are provided. An example memory includes M memory banks and a peripheral circuit including a control signal synthesis circuit and a first read register. The control signal synthesis circuit includes input terminals and a first output terminal. Each input terminal is connected with one corresponding memory bank and the first output terminal is connected with the first read register. The control signal synthesis circuit is configured to receive control signals through input terminals and output an overall control signal through the first output terminal. A path from each input terminal to the first output terminal in the control signal synthesis circuit has a same length. The first read register is configured to receive the overall control signal and data read from at least one of the M memory banks and output the read data based on the overall control signal.

Abstract: Methods for input/output voltage training of a three-dimensional (3D) memory device can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

Abstract: Memories, operation methods and memory systems are provided. An example memory includes M memory banks and a peripheral circuit including a control signal synthesis circuit and a first read register. The control signal synthesis circuit includes input terminals and a first output terminal. each input terminal is connected with one corresponding memory bank and the first output terminal is connected with the first read register. The control signal synthesis circuit is configured to receive control signals through input terminals and output an overall control signal through the first output terminal. A path from each input terminal to the first output terminal in the control signal synthesis circuit has a same length. The first read register is configured to receive the overall control signal and data read from at least one of the M memory banks and output the read data based on the overall control signal.

Abstract: Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may transmit, to a base station, a UE capability to receive a first portion of a tracking reference signal (TRS) and a second portion of the TRS, the first portion and the second portion associated with a TRS pattern. The UE may receive, from the base station, an indication of the TRS pattern, where the TRS pattern includes the first portion of the TRS pattern and the second portion of the TRS pattern. The UE may receive one or more TRSs according to the first portion of the TRS pattern and the second portion of the TRS pattern.

Abstract: Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

Abstract: Examples of the present disclosure provide memory devices and an operation method thereof. The memory device includes: a memory cell array; a control logic circuit coupled with the memory cell array and configured to receive a command address signal, output a first control signal at a first time instant, and output a second control signal at a second time instant, wherein the first time instant is different from the second time instant; and a clock generation circuit configured to receive a first clock signal, the first control signal and the second control signal, be pre-charged according to the first control signal, and perform frequency division processing on the first clock signal according to the second control signal to output a second clock signal, wherein the first clock signal is different from the second clock signal.

Abstract: Methods, systems, and devices for wireless communications are described. Generally, the described techniques provide for determining shared resources associated with one or more user equipments (UEs) for sidelink communications, including control resources and data resources. A first UE may transmit a sidelink request to reserve a subset of data resources to a second UE, and may monitor for one or more sidelink responses indicating a positive sidelink response to the sidelink request, a negative sidelink response to the sidelink request, or both. The second UE may transmit a positive sidelink response if it is available for a data transmission. A third UE may transmit a negative sidelink response if it objects to the data transmission. The first UE may determine, based on monitoring for the one or more sidelink responses, whether to transmit a sidelink confirmation indicating a reservation of the subset of the data resources to the second UE.

Abstract: Memories, operation methods and memory systems are provided. An example memory includes M memory banks and a peripheral circuit including a control signal synthesis circuit and a first read register. The control signal synthesis circuit includes input terminals and a first output terminal. each input terminal is connected with one corresponding memory bank and the first output terminal is connected with the first read register. The control signal synthesis circuit is configured to receive control signals through input terminals and output an overall control signal through the first output terminal. A path from each input terminal to the first output terminal in the control signal synthesis circuit has a same length. The first read register is configured to receive the overall control signal and data read from at least one of the M memory banks and output the read data based on the overall control signal.

Abstract: Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.

Abstract: Aspects described herein relate to determining and/or scheduling resources for devices in view of cross-channel interference measured between the devices. In an aspect, a first user equipment (UE) can determine a signal measurement of a signal transmitted by a second UE in a first channel, determine, based at least in part on the signal measurement, a cross-channel interference parameter of interference experienced by the first UE, and transmit, to a serving base station that serves the first UE, an indication of the cross-channel interference parameter. In another aspect, a base station can determine a cross-channel interference parameter of interference experienced by a first UE in at least a first channel, based on a signal transmitted by a second UE in a second channel, and can schedule communications for the first UE based at least in part on the cross-channel interference parameter.

Abstract: Example implementations include a method, apparatus and computer-readable medium of wireless communication over a sidelink between a first user equipment (UE) and a second UE. The first UE may receive, from a base station, a sidelink resource configuration indicating physical sidelink control channel (PSCCH)/physical sidelink shared channel (PSSCH) occasions on which to monitor a PSCCH for a grant from a second UE. The first UE may determine an active time for monitoring the PSCCH based on a discontinuous reception (DRX) mode for a link with the base station, the DRX mode including an active state in which a physical downlink control channel (PDCCH) is monitored and an inactive state in which the PDCCH is not monitored. The first UE may monitor the PSCCH during one or more of the PSCCH/PSSCH occasions that coincide with the active time.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first node may transmit, to a second node on a beamformed link from the first node to the second node, a first signal, wherein the first node and the second node are associated with common timing; determine whether a second signal, based at least in part on the first signal, is received on a beamformed link from the second node to the first node; and transmit a third signal based at least in part on receiving the second signal or perform a sidelink beam failure recovery procedure based at least in part on determining that the second signal is not received. Numerous other aspects are provided.

Abstract: A method of wireless communication by a first sidelink UE measures multiple reference signals periodically transmitted by a second sidelink UE using multiple receive beams corresponding to reference signals in response to a beam failure declared by the first UE. The method also selects one of the reference signals that satisfies a condition. The method further includes notifying the second sidelink UE of the selected reference signal using a beam corresponding to the selected reference signal. Another method of wireless communications by a first sidelink UE includes periodically transmitting, to a second sidelink UE, multiple beam failure recovery (BFR) reference signals across multiple transmit beams. The method also includes receiving, from the second sidelink UE, an indication of a selected beam for communications between the first sidelink UE and the second sidelink UE. The method notifies the second sidelink UE of successful beam failure recovery.

Abstract: Methods, systems, and devices for wireless communications are described. For example, the described techniques provide for configuring sidelink beam failure detection reference signals for determining beam failures on a sidelink between a first sidelink user equipment (UE) and a second sidelink UE. The first UE may determine a first set of sidelink beam failure detection reference signals to transmit to the second UE and a second set of sidelink beam failure detection reference signals to receive from the second UE. The first UE may transmit the first set to the second UE using a set of sidelink transmit beams. The first UE may further monitor for the determined second set using a set of sidelink receive beams. Based on the first and second set of sidelink beam failure detection reference signals, the first and second UE may communicate over the sidelink.

Abstract: Methods and apparatus for wireless communication by a first user-equipment (UE). The method generally includes monitoring for signaling from a second UE during a DRX cycle associated with a DRX configuration for at least one of the first UE or the second UE, determining whether the first UE and the second UE are within range for communication based on the monitoring, and taking one or more actions based on the determination.

Abstract: Certain aspects of the present disclosure provide techniques for selecting and indicating a quasi colocation (QCL) source signal for sidelink (SL) communications. For example, a scheduling node may select from multiple candidates a signal for a first user equipment (UE) to use as a spatial QCL source for a receive (RX) or transmit (TX) beam to use for communicating with a second UE on a SL interface. The scheduling node may then signal the first UE an indication of the selection of the signal.