Patents by Inventor Ling Gao

Ling Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230122792
    Abstract: The invention relates to the technical field of bioengineering and provides a method for improving the specificity and affinity of an aptamer. The method includes: S1, screening a target of an aptamer from a compound information database by virtual computing; S2, verifying the screening result in Step S1 through experiments; S3, performing virtual saturation mutation on a site of the aptamer, and screening out a mutation site of the aptamer; S4, performing base substitution to the mutation site of the aptamer; and S5, detecting the binding parameter of the aptamer after base substitution with the target screened in Step S1, and selecting an aptamer with improved specificity and affinity after base substitution. An efficient molecular design-guided method is developed by computer rational calculation, to improve the specificity and binding affinity of the aptamer by directional modification. The present invention is of great significance for the practical application of aptamers.
    Type: Application
    Filed: January 13, 2022
    Publication date: April 20, 2023
    Inventors: Xiaole XIA, Yue ZHANG, Ling GAO, Mengfei LONG, Qingtong ZHOU, Jingwen ZHOU
  • Publication number: 20230008005
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Patent number: 11428739
    Abstract: A device for rapidly detecting energy efficiency of a permanent magnet synchronous motor includes a test platform, an energy circulation device, and a data synchronous acquisition module, the test platform being fixedly connected to support legs via threads, an upper end surface of the test platform being provided with baffles to define a motor mounting tank, a bolt hole being provided in a surface of an outer baffle of the motor mounting tank, the energy circulation device being mounted on a fixed baffle on one end of the motor mounting tank, a second intelligent power analyzer, a first intelligent power analyzer, and a temperature inspection instrument being sequentially mounted on an upper surface of a tail end on a right side of the test platform, and the data synchronous acquisition module being provided on one end of an inner wall of the motor mounting tank.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: August 30, 2022
    Assignee: JINLING HAIGUAN TECHNICAL CENTER
    Inventors: Ying Hong, Wei An, Jiadan Wei, Yangyun Wu, Junwei Xu, Ling Gao, Ke Chen, Jinling Wang, Chen Tang, Jiansong Chen
  • Publication number: 20220252669
    Abstract: A device for rapidly detecting energy efficiency of a permanent magnet synchronous motor includes a test platform, an energy circulation device, and a data synchronous acquisition module, the test platform being fixedly connected to support legs via threads, an upper end surface of the test platform being provided with baffles to define a motor mounting tank, a bolt hole being provided in a surface of an outer baffle of the motor mounting tank, the energy circulation device being mounted on a fixed baffle on one end of the motor mounting tank, a second intelligent power analyzer, a first intelligent power analyzer, and a temperature inspection instrument being sequentially mounted on an upper surface of a tail end on a right side of the test platform, and the data synchronous acquisition module being provided on one end of an inner wall of the motor mounting tank.
    Type: Application
    Filed: December 14, 2021
    Publication date: August 11, 2022
    Inventors: YING HONG, WEI AN, JIADAN WEI, YANGYUN WU, JUNWEI XU, LING GAO, KE CHEN, JINLING WANG, CHEN TANG, JIANSONG CHEN
  • Patent number: 11232696
    Abstract: Concealed mark preparation with core-shell luminosphores for customs security check system and application thereof, to address that infrared luminescent materials have not been used in senseless customs clearance field, absorption cross sections of infrared luminescent materials currently available are not big enough, and upconversion luminescence intensity thereof is low, consequently, the luminescent marks are not clear enough to recognize marked abnormal luggage, and provide a following solution: step 1: preparing TiQ2; step 2: preparing Ag@TiO2 composite nanoparticles; step 3: preparing Ag@TiQ2@NaYF4:Yb3+, Er3+ luminescent nanoparticles; step 4: making concealed luggage marks.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: January 25, 2022
    Assignees: JINLING HAIGUAN TECHNICAL CENTER, JIANGSU YANGTZE TESTING AND CERTIFICATION CO., LTD.
    Inventors: Ying Hong, Rong Gao, Jinling Wang, Guosong Chen, Yuanyuan Zhu, Jing Fang, Ling Gao, Weijian Shen, Wei An, Jiansong Chen
  • Patent number: 11209689
    Abstract: A display panel includes a first substrate, a second substrate, and spacers. The first substrate includes a light-shielding layer having a matrix portion and widened portions, and each widened portion is disposed at an intersection of at least one column and at least one row of the matrix portion. The second substrate is disposed opposite to the first substrate. The spacers are disposed on the first substrate. Each spacer is covered with each widened portion respectively, and an end of each spacer abuts against a surface of the second substrate. A slidable scope on the surface of the second substrate, within which the end of each spacer abuts against the second substrate, is not greater than coverage of a corresponding widened portion.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: December 28, 2021
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Ling Gao
  • Publication number: 20210257360
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Application
    Filed: September 15, 2020
    Publication date: August 19, 2021
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Publication number: 20210257462
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Application
    Filed: December 18, 2020
    Publication date: August 19, 2021
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Publication number: 20210249312
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung CHANG, Jiun-Ming KUO, Che-Yuan HSU, Pei-Ling GAO, Chen-Hsuan LIAO
  • Publication number: 20210202346
    Abstract: A packaging structure includes: a substrate provided with a through-cavity penetrating up and down, and a metal heat sink on a front surface of the substrate; a bonding chip mounting area and a first passive element mounting area on the front surface, and a flip chip mounting area, a second passive element mounting area and a pin lead mounting area are provided on a back surface of the substrate; a first sealing ring located at the periphery of the bonding chip mounting area and the first passive element mounting area; a first cover plate packaged on the first sealing ring; a second sealing ring located at the periphery of the flip chip mounting area and the second passive element mounting area with the pin lead mounting area being located at the periphery of the second sealing ring; and a second cover plate packaged on the second sealing ring.
    Type: Application
    Filed: March 1, 2021
    Publication date: July 1, 2021
    Inventors: Bo Peng, Ling Gao, Xiaojun Zhang, Yang Liu, Qiang Duan, Dapeng Bi, Congge Lu
  • Publication number: 20200400989
    Abstract: A display panel, a display module and an electronic device are provided. The display panel includes an array substrate and a color filter. The array substrate includes a first substrate and a first common electrode layer disposed on the first substrate. The color filter substrate is disposed against the array substrate. The color filter substrate includes a second substrate and a spacer on the second substrate. The spacer includes a first spacer and a second spacer. A height of the first spacer is higher than or equal to a height of the second spacer.
    Type: Application
    Filed: November 15, 2018
    Publication date: December 24, 2020
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Ling GAO
  • Publication number: 20200301196
    Abstract: A display panel includes a first substrate, a second substrate, and spacers. The first substrate includes a light-shielding layer having a matrix portion and widened portions, and each widened portion is disposed at an intersection of at least one column and at least one row of the matrix portion. The second substrate is disposed opposite to the first substrate. The spacers are disposed on the first substrate. Each spacer is covered with each widened portion respectively, and an end of each spacer abuts against a surface of the second substrate. A slidable scope on the surface of the second substrate, within which the end of each spacer abuts against the second substrate, is not greater than coverage of a corresponding widened portion.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 24, 2020
    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Ling GAO
  • Publication number: 20200292863
    Abstract: A display panel includes a first substrate, a second substrate, and spacers. The second substrate is disposed opposite to the first substrate. Hollow portions are disposed on a surface of the second substrate. The spacers are disposed on the first substrate, and an end of each spacer, far from the first substrate, abuts against each hollow portion on the second substrate respectively.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 17, 2020
    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Ling GAO
  • Patent number: 10600811
    Abstract: The invention provides a TFT array substrate and LCD panel. The TFT array substrate adopts a Notch design, with a base substrate disposed with a groove at one end. The base substrate comprises a functional area and a peripheral area located outside the functional area, and the planarization layer on the base substrate has a first portion corresponding to the functional area, wherein the first portion adjacent to the groove is provided with at least one pit, and the depth of the pit is smaller than the thickness of the first portion. When the TFT array substrate and the CF substrate are assembled, after the LC is injected between TFT array substrate and CF substrate, the LC accumulation generated in the first portion of the planarization layer near the groove during diffusion is in the pit, thereby making the LC layer thickness uniform and improved quality of LCD panel.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 24, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ling Gao, Xiaojiang Yu
  • Publication number: 20190326331
    Abstract: The invention provides a TFT array substrate and LCD panel. The TFT array substrate adopts a Notch design, with a base substrate disposed with a groove at one end. The base substrate comprises a functional area and a peripheral area located outside the functional area, and the planarization layer on the base substrate has a first portion corresponding to the functional area, wherein the first portion adjacent to the groove is provided with at least one pit, and the depth of the pit is smaller than the thickness of the first portion. When the TFT array substrate and the CF substrate are assembled, after the LC is injected between TFT array substrate and CF substrate, the LC accumulation generated in the first portion of the planarization layer near the groove during diffusion is in the pit, thereby making the LC layer thickness uniform and improved quality of LCD panel.
    Type: Application
    Filed: September 19, 2018
    Publication date: October 24, 2019
    Inventors: Ling Gao, Xiaojiang Yu
  • Patent number: 9520253
    Abstract: A button is mounted to a housing of an electronic device, the button includes a pressing body and a sealed body. The pressing body is mounted to the housing. The sealed body is coupled to the pressing body, the sealed body defines a slot around an external peripheral wall and forms two opposite elastic walls, the two elastic walls resist to the pressing body and the housing, respectively. An electronic device and a button arrangement employing the button are also disclosed.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 13, 2016
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventor: Yan-Ling Gao
  • Patent number: 9435747
    Abstract: A reflectance spectroscopy measuring and sampling system for gemstone testing is disclosed. The system includes a first light source (1), a second light source (2), a light filtering element, an integrating sphere (S), an optical fiber (9), a spectroscopic detection module (10), an analog-digital conversion module (11) and a data processing terminal (12), wherein the integrating sphere (S) is provided with an entrance port, a sampling opening (6) and a reflected light exit port (7). A reflectance spectroscopy measuring and sampling method for gemstone testing is also disclosed. The system and the method have an excellent performance and can be widely used in the gemstone identification.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 6, 2016
    Assignee: Biaoqi Electronics Technology, Co., Ltd.
    Inventors: Guangjun Song, Xiangli Zheng, Jianfeng Wu, Ling Gao
  • Patent number: 9356641
    Abstract: A protective case includes a main housing and a cover. The main housing includes a wire arranging portion with a first frame, a second frame, and a third frame. The first frame and the second frame are diagonally positioned each other, and the third frame are positioned at one side of the second frame. The cover is detachable from the main housing for covering the wire arranging portion.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 31, 2016
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (Hong Kong) Limited
    Inventor: Yan-Ling Gao
  • Publication number: 20150233839
    Abstract: A reflectance spectroscopy measuring and sampling system for gemstone testing is disclosed. The system includes a first light source (1), a second light source (2), a light filtering element, an integrating sphere (S), an optical fiber (9), a spectroscopic detection module (10), an analog-digital conversion module (11) and a data processing terminal (12), wherein the integrating sphere (S) is provided with an entrance port, a sampling opening (6) and a reflected light exit port (7). A reflectance spectroscopy measuring and sampling method for gemstone testing is also disclosed. The system and the method have an excellent performance and can be widely used in the gemstone identification.
    Type: Application
    Filed: January 16, 2013
    Publication date: August 20, 2015
    Applicant: BIAOQI ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Guangjun Song, Xiangli Zheng, Jianfeng Wu, Ling Gao
  • Publication number: 20150055314
    Abstract: A mounting assembly for a chip card used in a portable electronic device includes a cover, an operating element, and a receiving member for receiving the chip card. One end of the operating element is slidably received in the cover, and the other end of the operating element is elastically resisted between the receiving member and the cover and is connected to the receiving member. The cover is pressed to expose the operating element and the operating element is pulled to allow the receiving member to move out of the portable electronic device.
    Type: Application
    Filed: October 23, 2013
    Publication date: February 26, 2015
    Applicants: FIH (Hong Kong) Limited, SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD.
    Inventor: YAN-LING GAO