Patents by Inventor Ling Liu

Ling Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250148705
    Abstract: According to one embodiment, a method, computer system, and computer program product for physical object tracking in virtual reality is provided. The present invention may include receiving input from a user identifying a specific physical object during a virtual reality session in a virtual reality environment; identifying the specific physical object in the physical proximity of the user; tracking the location of the specific physical object relative to the user; and responsive to receiving a command from the user, displaying the specific physical object to the user through a portal in the virtual reality environment.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Raymund Lin, Nan Chen, Li Na Wang, Ye Chuan Wang, Ju Ling Liu
  • Patent number: 12289208
    Abstract: The present invention provides an optimization method and system for minimizing network energy consumption based on traffic grooming. The method includes: generating a set of service requests in an elastic optical network, and calculating a reachable node set of shortest paths from source to destination nodes for each service request; establishing a virtual reachable path in the reachable node set of shortest paths; and establishing a target function of an integer linear programming model of the minimizing network energy consumption, and sequentially determining whether a bandwidth capacity constraint of a single spectrum slot, a path uniqueness constraint, a spectrum allocation constraint, and an optical regenerator quantity constraint are satisfied, where if all constraints are satisfied, the service request is successfully established, or if any of the constraints is not satisfied, the service request fails to be established. The present invention helps to improve the energy efficiency of service requests.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: April 29, 2025
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Bowen Chen, Yunfei Jiang, Qi Chen, Weike Ma, Ling Liu, Gangxiang Shen, Mingyi Gao, Lian Xiang, Hong Chen
  • Publication number: 20250132246
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Inventors: Yi Ling Liu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12280070
    Abstract: A drug for the prevention or treatment of sepsis is provided. The drug comprises an exosome containing a circRNA MOTOR, and a nucleotide sequence corresponding to the circRNA MOTOR is shown in SEQ ID NO: 1.
    Type: Grant
    Filed: November 21, 2024
    Date of Patent: April 22, 2025
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Wei Huang, Haibo Qiu, Ke Fang, Jianfeng Xie, Ling Liu, Yi Yang, Ran Yang
  • Publication number: 20250126848
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Wen-Chih CHIANG, Yi-Ling LIU, Huai-jen TUNG, Keng-Ying LIAO
  • Publication number: 20250082666
    Abstract: A drug for the prevention or treatment of sepsis is provided. The drug comprises an exosome containing a circRNA MOTOR, and a nucleotide sequence corresponding to the circRNA MOTOR is shown in SEQ ID NO: 1.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Wei HUANG, Haibo QIU, Ke FANG, Jianfeng XIE, Ling LIU, Yi YANG, Ran YANG
  • Publication number: 20250086087
    Abstract: Computer implemented methods, systems, and computer program products include program code executing on a processor(s) obtain factor(s) relevant to a given resource. The program code determines relationships between the factor(s). Based on parameters comprising the relationships, the program code identifies, from a search space, configuration(s) for resource(s) and configuration(s) for workload(s) in the computing environment. The program code executes, based on a pre-defined policy, a test: a workload configured according to a configuration in a system under test instance configured according to a configuration. The program code obtains performance measurements for the test in the system under test instance. The program code utilizes the performance measurements to update a known data set.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 13, 2025
    Inventors: Ying MO, Wu DI, Xing TIAN, Qing Zhi YU, Nan CHEN, Ju Ling LIU
  • Publication number: 20250068535
    Abstract: In several aspects for generation of high quality synthetic observability data for computing systems, traces and logs from a system are collected as a seed dataset. Multiple conditional variational autoencoder (VAE) models are trained using the seed dataset for learning association between the traces and the logs. Synthetic traces and logs are generated using the multiple CVAE models while retaining the association between the traces and the logs for the synthetic traces and logs.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 27, 2025
    Inventors: Ying Mo, Wu Di, Xing Tian, Qing Zhi Yu, Nan Chen, Ju Ling Liu
  • Publication number: 20250049300
    Abstract: Disclosed is a dual-channel instrument guiding device for hysteroscope. The dual-channel instrument guiding device for hysteroscope is provided with a cavity dividing piece provided in an operation sleeve thereof. The cavity dividing piece divides the interior of the operation sleeve into three channels isolated from one another. One of the channels is used as a lens channel for a hysteroscopic lens to pass through, and the remaining two channels are used as instrument channels for surgical instruments to pass through. During actual use, different instruments can be introduced into two instrument channels simultaneously to perform surgical operation on a lesion area in a human body cavity, and the problem that the existing hysteroscope cannot achieve the mutual operation of multiple instruments at the lesion of the cavity simultaneously is solved.
    Type: Application
    Filed: April 29, 2024
    Publication date: February 13, 2025
    Inventor: Ling Liu
  • Publication number: 20250045190
    Abstract: A computer-implemented method, a computer system, and a computer program product for generating an automation test script. Existing testing documents of a product under test can be acquired. A testing topology describing steps, containers, elements and actions of the test can be generated by extracting keywords in the existing test documents, wherein each element defines a user interface (UI) element of the product, each action defines an action attribute for an associated UI element, each container defines an operation area containing one or more UI elements, and each step defines one or more operations for one or more actions associated with one or more UI elements. An automation test script for the product can be generated based on the testing topology.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 6, 2025
    Inventors: Dong Chen, Jia Chan Shen, Ju Ling Liu, Ting Ting Zhan
  • Publication number: 20250046756
    Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
  • Patent number: 12216901
    Abstract: A method for selecting an application and associated operational guidance to utilize on a mobile device is disclosed. In one embodiment, such a method identifies a selected environment of interest. Within the selected environment, the method identifies one or more applications that are commonly utilized by users within the selected environment and documents the one or more applications. The method detects physical entry of a particular user into the selected environment and, in response to detecting the entry, automatically notifies the particular user of the one or more applications that are commonly utilized within the selected environment. In certain embodiments, the method enables the user to quickly launch the one or more applications and/or provides operational guidance to the user with regard to using the one or more applications. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: February 4, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiang Wei Li, Dong Chen, Ye Chuan Wang, Ting Ting Zhan, Ju Ling Liu, Yu An, Wei Yan
  • Patent number: 12218253
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Grant
    Filed: April 15, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Yi-Ling Liu, Huai-Jen Tung, Keng-Ying Liao
  • Publication number: 20250038074
    Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: January 30, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250029880
    Abstract: Seal ring structures having alignment marks are disclosed herein. An exemplary semiconductor structure includes a seal ring surrounding a circuit region and a corner seal ring (CSR) structure at an interior corner of the seal ring. The CSR structure includes a bridge section between a first edge and a second edge of the seal ring, an L-shaped section between the seal ring and the bridge section and between the first edge and the second edge of the seal ring, a first area between the seal ring and the L-shaped section, and a second area between the L-shaped section and the bridge section. The seal ring includes a first top metal line and an aluminum pad (AP) disposed over and connected to the first top metal line. The L-shaped section includes a second top metal line having an L-shape. The first area and the second area are free of dummy AP.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventor: Szu-Ling Liu
  • Publication number: 20250029922
    Abstract: A substrate is provided, wherein the substrate includes a device layer, and a logo region is defined in a peripheral region of the substrate. An interconnect structure is formed over the device layer. A first conductive feature and at least one second conductive feature are formed in the interconnect structure, wherein the first conductive feature is recognizable as a first identification mark, and the at least one second conductive feature is disposed between different portions of the first conductive feature. A third conductive feature is formed at a first elevation over a second elevation of the first conductive feature, wherein the third conductive feature overlaps the first conductive feature vertically and is recognizable as a second identification mark, and a space other than the third conductive feature in the logo region at the first elevation is filled with a dielectric material.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventor: SZU-LING LIU
  • Publication number: 20250023087
    Abstract: A wound electrode assembly, a battery cell, a battery, a power consuming device, and a winding apparatus are disclosed. The wound electrode assembly includes: an electrode plate; and a separator attached to the electrode plate and located in a bent region of the electrode plate, the separator losing viscosity between the separator and the electrode plate within a preset time. With the solution described hereine performance of the battery can be improved.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Ling LIU, Caixia HUANG
  • Publication number: 20240419464
    Abstract: Disability-related information of a user of a computing device can be acquired, the computing device can present a scene with user interface elements to the user. An accessibility requirement of the user can be identified based on the acquired disability-related information of the user. A processing routine can be determined from a plurality of processing routines stored in a routine library based on the accessibility requirement of the user. One or more of the user interface elements of the scene can be modified using the determined processing routine. The scene with the modified one or more of the user interface elements can be presented to the user through the computing device.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 19, 2024
    Inventors: Dong Chen, Ye Chuan Wang, Xiang Wei Li, Ju Ling Liu, Yu An, Wei Yan, Ting Ting Zhan
  • Patent number: 12169218
    Abstract: Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: December 17, 2024
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ling Liu, Robert Gee
  • Publication number: 20240393650
    Abstract: An electronic device includes a scan line disposed on a first substrate and extending along a first direction; a conductive element disposed on the first substrate and a portion of the conductive element extending along a second direction different from the first direction; and an active layer disposed between the conductive element and the first substrate. In a top view, the active layer includes a first connecting region electrically connected to the conductive element through a first via hole; a first overlapping region overlapping a portion of the scan line; first region disposed between the first connecting region and the first overlapping region, wherein the first region extends along the second direction and overlaps the portion of the conductive element; and a turning region between the first overlapping region and the first region.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Inventors: Hsing-Yi LIANG, Kuei-Ling LIU, Te-Yu LEE