Patents by Inventor Ling Pan

Ling Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240241126
    Abstract: The present invention provides a biochip for tracking postoperative recurrence status of a patient with lung adenocarcinoma. The biochip comprises a bare plate layer, the bare plate layer comprises a sensing electrode, and the sensing electrode comprises a biological agent capable of measuring an expression amount of a GPNMB gene. The present invention further provides a method for tracking the postoperative recurrence status of a patient with lung adenocarcinoma. The method comprises the following steps: step one, providing a sample from a patient with lung adenocarcinoma; step two: contacting the sample with a carrier capable of detecting an expression amount of a GPNMB gene; and step three: analyzing a change of the expression amount of the GPNMB gene to track the postoperative recurrence status of the patient with lung adenocarcinoma.
    Type: Application
    Filed: July 14, 2023
    Publication date: July 18, 2024
    Inventors: Szu-Hua Pan, Yuan-Ling Hsu, Ching-Wen Li, How-Wen Ko, Chung-Lieh Hung
  • Publication number: 20240232520
    Abstract: An electronic device and a method for editing personal information are provided. The electronic device includes a display and a processor. The display is configured to display a personal information display area, a first item template and a second item template, and the personal information display area and the first item template are separated by a boundary. The processor is configured to: receive the personal information including a first content, wherein the first item template and the second item template do not present the first content of the personal information; receive a first input operation to move the first item template to the personal information display area to generate a first information item corresponding to the first item template; and present the first content of the personal information by the first information item after moving the first item template to the personal information display area according to the first input operation.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: CHUN-YI LIU, CHENG-MIN TING, CHUG-LING PAN
  • Publication number: 20240234403
    Abstract: A microelectronic device package includes a microelectronic device coupled to a substrate. The microelectronic device package further includes a stack of semiconductor dies positioned over the microelectronic device. The microelectronic device package also includes an interposer positioned between the microelectronic device and the stack of semiconductor dies. The interposer includes a conductive structure electrically connecting the microelectronic device and a ground circuit of the substrate. The interposer further includes an insulative structure positioned between the conductive structure and the stack of semiconductor dies.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Inventors: Seng Kim Dalson Ye, Kelvin Tan Aik Boo, Hong Wan Ng, See Hiong Leow, Ling Pan
  • Publication number: 20240234390
    Abstract: A microelectronic device package includes a stack of semiconductor dies positioned over a substrate. The microelectronic device package further includes an interposer structure coupled to the stack of semiconductor dies. The microelectronic device package further includes an electronic component directly coupled to the interposer structure and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Inventors: Seng Kim Dalson Ye, Kelvin Tan Aik Boo, Hong Wan Ng, See Hiong Leow, Ling Pan
  • Publication number: 20240203842
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface, a second substrate surface arranged opposite to the first substrate surface, and a substrate edge that extends from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, wherein each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 20, 2024
    Inventors: Seng Kim YE, Kelvin Aik Boo TAN, Hong Wan NG, Chin Hui CHONG, Ling PAN, See Hiong LEOW
  • Publication number: 20240193042
    Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 13, 2024
    Inventors: Jun Wang, De Hua Guo, Jia Ling Pan, Kui Ding, Kun Liu
  • Publication number: 20240194547
    Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 13, 2024
    Inventors: Ling Pan, Seng Kim Ye, Hong Wan Ng, Kelvin Aik Boo Tan, See Hiong Leow
  • Publication number: 20240194630
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 13, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240162206
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Seng Kim YE, Hong Wan NG, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN
  • Publication number: 20240162207
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 16, 2024
    Inventors: Kelvin Aik Boo TAN, Hong Wan NG, See Hiong LEOW, Seng Kim YE, Ling PAN
  • Publication number: 20240145457
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Inventors: Faxing CHE, Yeow Chon ONG, Wei YU, Ling PAN
  • Patent number: 11966693
    Abstract: An electronic device and a method for editing a resume are provided. The electronic device includes a display, a transceiver, a storage medium, and a processor. The processor receives personal information through the transceiver, and inputs the personal information into a plurality of item templates to generate an item template with personal information and a blank item template without personal information corresponding to the plurality of item templates. The processor displays the plurality of item templates through the display, and receives a first input operation to add a first item template and a second item template in the plurality of item templates to a resume display area to generate a resume. The processor outputs the resume through the transceiver.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 23, 2024
    Assignee: TRANTOR TECH, INC.
    Inventors: Chun Yi Liu, Cheng-Min Ting, Chun Ling Pan
  • Publication number: 20240071881
    Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Wei Yu, Kelvin Tan Aik Boo
  • Publication number: 20240074048
    Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Hong Wan Ng, Kelvin Tan Aik Boo, Seng Kim Ye, See Hiong Leow
  • Publication number: 20240071980
    Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240071990
    Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240071869
    Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Patent number: D1017796
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: March 12, 2024
    Inventor: Ling Pan
  • Patent number: D1018838
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: March 19, 2024
    Inventor: Ling Pan
  • Patent number: D1024311
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: April 23, 2024
    Inventor: Ling Pan