Patents by Inventor Ling Pan

Ling Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142768
    Abstract: An information handling system includes an air mover and a management controller configured to determine an airflow direction of the air mover. The air mover includes an enclosure base and a gear disposed within the enclosure base. The gear is configured to rotate an outlet frame, and the outlet frame is configured to rotate within the enclosure base. The outlet frame includes a nozzle structure that is configured to guide the airflow direction according to a determination of the management controller.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Inventors: Jer-Yo Lee, Yu-Min Huang, Chi-Yung Chiang, Mei-Ling Pan, Ya Chen Chang, Jung Jung Wang, Huan-Chun Wu, Po-Fei Tsai, Hao Wu Yang
  • Patent number: 12255217
    Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wen Huang, Chun-Lin Fang, Kuan-Ling Pan, Ping-Hao Lin, Kuo-Cheng Lee, Cheng-Ming Wu
  • Publication number: 20250086061
    Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
    Type: Application
    Filed: August 13, 2024
    Publication date: March 13, 2025
    Inventors: Jun Wang, De Hua Guo, Jia Ling Pan, Kui Ding, Kun Liu
  • Publication number: 20240404995
    Abstract: An apparatus includes selectable a circuit placement mechanism configured to support two or more different circuit layouts. The circuit placement mechanism may include an overlap of electrical connections associated with the two or more circuit layouts and joined through an etch back selector. The etch back selector may enable the apparatus to function according to a selected one of the two or more different circuit layouts.
    Type: Application
    Filed: April 25, 2024
    Publication date: December 5, 2024
    Inventors: Chin Hui Chong, Hong Wan Ng, See Hiong Leow, Ling Pan, Seng Kim Ye, Kelvin Tan Aik Boo
  • Publication number: 20240332216
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; at least one die arranged on the first substrate surface; a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and covers at least part of the first substrate surface; a plurality of conductive interconnect structures coupled to the second substrate surface, wherein the plurality of conductive interconnect structures are electrically coupled to the at least one die via the circuit substrate; and at least one molded compound structure arranged on the second substrate surface, wherein the at least one molded compound structure is configured to reduce a coplanarity of the plurality of conductive interconnect structures.
    Type: Application
    Filed: March 15, 2024
    Publication date: October 3, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Kelvin Aik Boo TAN, Seng Kim YE, Ling PAN, Chin Hui CHONG
  • Publication number: 20240312890
    Abstract: At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.
    Type: Application
    Filed: February 15, 2024
    Publication date: September 19, 2024
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, See Hiong Leow, Ling Pan, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20240304598
    Abstract: A microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. The first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. The wire contacts the first pad of the first die and the second pad of the second die. Memory device packages and electronic systems are also disclosed.
    Type: Application
    Filed: January 26, 2024
    Publication date: September 12, 2024
    Inventors: Chin Hui Chong, Seng Kim Dalson Ye, Hong Wan Ng, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Patent number: 12072767
    Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: August 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jun Wang, De Hua Guo, Jia Ling Pan, Kui Ding, Kun Liu
  • Patent number: 12075583
    Abstract: An electronic device housing, an electronic device and a compound body are provided. The electronic device housing comprises a frame; a sealing layer, disposed on at least a part of an outer surface of the frame, and including a plurality of sub-sealing layers laminated in sequence; and a back case, attached to the frame by the sealing layer, wherein two adjacent sub-sealing layers have different compositions.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 27, 2024
    Assignee: BYD COMPANY LIMITED
    Inventors: Lan Ma, Haiyan Jin, Ling Pan, Na Yu, Liang Chen
  • Publication number: 20240282751
    Abstract: A variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. A substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. The downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 22, 2024
    Inventors: Ling Pan, Seng Kim Ye, Kelvin Aik Boo Tan, Hong Wan Ng, See Hiong Leow, Chong C. Hui
  • Publication number: 20240268132
    Abstract: Some implementations described herein are directed to a semiconductor die package including a stacked die arrangement. The semiconductor die package includes one or more legged support structures between respective overhang portions of the stacked die arrangement and a substrate of the semiconductor die package. The one or more legged support structures may reduce a likelihood of the respective overhang portions deflecting during manufacturing of the semiconductor die package. By reducing the likelihood of the overhang portions deflecting, a quality and reliability of the semiconductor die package may be improved.
    Type: Application
    Filed: January 4, 2024
    Publication date: August 8, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Chin Hui CHONG, Ling PAN, Kelvin Aik Boo TAN, Seng Kim YE
  • Patent number: 12053570
    Abstract: A nasal aspirator suction bin assembly comprises a suction bin base, which has a first connecting end connected with a host and a second connecting end connected with a suction bin cover; after the suction bin base is connected with the suction bin cover, a cavity is formed therein; the middle of the suction bin base is provided with an outlet tube, which runs through the suction bin base and extends into the cavity; the upper end of the suction bin cover is provided with a suction tube, which runs through the suction bin cover and extends into the cavity; a bracket is arranged in the cavity, and the bracket comprises a bracket tube which can be inserted on the outlet tube and a baffle arranged at the other free end of the bracket tube, and at least one air hole is arranged on the bracket tube to keep the suction tube and the outlet tube in communication all the time; the cavity is used to store the inhaled nasal fluid.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: August 6, 2024
    Inventor: Ling Pan
  • Publication number: 20240234390
    Abstract: A microelectronic device package includes a stack of semiconductor dies positioned over a substrate. The microelectronic device package further includes an interposer structure coupled to the stack of semiconductor dies. The microelectronic device package further includes an electronic component directly coupled to the interposer structure and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Inventors: Seng Kim Dalson Ye, Kelvin Tan Aik Boo, Hong Wan Ng, See Hiong Leow, Ling Pan
  • Publication number: 20240232520
    Abstract: An electronic device and a method for editing personal information are provided. The electronic device includes a display and a processor. The display is configured to display a personal information display area, a first item template and a second item template, and the personal information display area and the first item template are separated by a boundary. The processor is configured to: receive the personal information including a first content, wherein the first item template and the second item template do not present the first content of the personal information; receive a first input operation to move the first item template to the personal information display area to generate a first information item corresponding to the first item template; and present the first content of the personal information by the first information item after moving the first item template to the personal information display area according to the first input operation.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: CHUN-YI LIU, CHENG-MIN TING, CHUG-LING PAN
  • Publication number: 20240234403
    Abstract: A microelectronic device package includes a microelectronic device coupled to a substrate. The microelectronic device package further includes a stack of semiconductor dies positioned over the microelectronic device. The microelectronic device package also includes an interposer positioned between the microelectronic device and the stack of semiconductor dies. The interposer includes a conductive structure electrically connecting the microelectronic device and a ground circuit of the substrate. The interposer further includes an insulative structure positioned between the conductive structure and the stack of semiconductor dies.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Inventors: Seng Kim Dalson Ye, Kelvin Tan Aik Boo, Hong Wan Ng, See Hiong Leow, Ling Pan
  • Publication number: 20240203842
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface, a second substrate surface arranged opposite to the first substrate surface, and a substrate edge that extends from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, wherein each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 20, 2024
    Inventors: Seng Kim YE, Kelvin Aik Boo TAN, Hong Wan NG, Chin Hui CHONG, Ling PAN, See Hiong LEOW
  • Publication number: 20240194547
    Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 13, 2024
    Inventors: Ling Pan, Seng Kim Ye, Hong Wan Ng, Kelvin Aik Boo Tan, See Hiong Leow
  • Publication number: 20240193042
    Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 13, 2024
    Inventors: Jun Wang, De Hua Guo, Jia Ling Pan, Kui Ding, Kun Liu
  • Publication number: 20240194630
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 13, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240162206
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Seng Kim YE, Hong Wan NG, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN