Patents by Inventor Ling Pan

Ling Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105136
    Abstract: An electronic device includes a display unit, a voltage generation unit, a grayscale adjustment unit, and an overdriving unit. The display unit has a relationship curve between the transmittance and the driving voltage. The relationship curve has a predetermined voltage value corresponding to the maximum transmittance. The voltage generation unit generates a first voltage according to a first grayscale, and generates a second voltage according to a second grayscale. The grayscale adjustment unit receives a first display grayscale value, and outputs the second grayscale value when the first display grayscale value is equal to the first grayscale. The overdriving unit overdrives the second voltage corresponding to the second grayscale to obtain a first target driving voltage, and it provides the first target driving voltage to the display unit.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 28, 2024
    Inventors: Syue-Ling FU, Yeh-Yi LAN, Cheng-Cheng PAN, Meng-Kun TSAI
  • Publication number: 20240103349
    Abstract: The present disclose discloses a micro-display optical engine including a micro-LED panel, a coolant, a thin lens, a metal frame, a connecting pillar and a projection lens; the micro-LED panel comprises a substrate, a number of pixel light-emitting micro-LED grains, a glass plate, a metal bracket, a sealing frame, a radiator, a filling adhesive and a transparent heat-conducting adhesive. The present disclose also discloses a single-engine, dual-engine and three-engine full-color projector. The present disclose has remarkable features such as relatively simple production, the ability to achieve preliminary productization, excellent thermal stability of heat dissipation, high contrast and color gamut, laying a certain foundation for the actual productization of the new micro-LED micro-display projection technology.
    Type: Application
    Filed: December 29, 2022
    Publication date: March 28, 2024
    Inventors: Ling Chen, Rao Chen, Yating Pan, Jie Wang
  • Publication number: 20240074048
    Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Hong Wan Ng, Kelvin Tan Aik Boo, Seng Kim Ye, See Hiong Leow
  • Publication number: 20240071869
    Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Publication number: 20240071990
    Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240071881
    Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Wei Yu, Kelvin Tan Aik Boo
  • Publication number: 20240071980
    Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240063135
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN
  • Publication number: 20240063168
    Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: See Hiong Leow, Hong Wan NG, Seng Kim Ye, Kelvin Aik Boo Tan, Ling Pan
  • Publication number: 20240063201
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a flip chip die electrically coupled to the substrate via a plurality of electrical connections, and a non-conductive film disposed between the flip chip die and the substrate. The non-conductive film may surround the plurality of electrical connections and mechanically couple the flip chip die to the substrate.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240057265
    Abstract: Substrates having stress-releasing features, and associated systems and methods are disclosed herein. In some embodiments, the substrate includes a core layer, a metallization layer formed on an outer surface of the core layer, and a solder mask formed over the metallization layer and the outer surface. The metallization layer can include at least one bond pad and the solder mask can include a first opening exposing the bond pad. The first opening can be surrounded by a bonding region of the solder mask that thermally interfaces with the bond pad and/or any conductive structure bonded thereon. The solder mask can also include one or more second openings adjacent the first opening. Each of the second openings provides space for the solder mask to expand into to release stress due to thermal expansions of the bond pad, the solder mask, and/or the conductive structure during manufacturing and/or operation.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Inventors: Kelvin Tan Aik Boo, Ling Pan
  • Publication number: 20240039185
    Abstract: Methods, systems, and devices for connection designs for memory systems are described. A memory system may include a package and a printed circuit board (PCB). An interface of the package may be coupled with the PCB via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the PCB, or both. The memory system may also include a set of latches that may secure the package in a fixed position relative to the PCB. That is, the set of springs may provide an electrical connection between the package and the PCB, and the set of latches may provide a mechanical connection between the package and the PCB. In some examples, the package, the PCB, or both, may include one or more connection structures configured to receive the latches.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Wei Yu, Ling Pan
  • Publication number: 20230402822
    Abstract: A manufacturing method of a semiconductor device includes: providing a semiconductor stack layer, wherein the semiconductor stack layer includes a first type semiconductor layer, a quantum well layer, and a second type semiconductor layer stacked in sequence; growing an aluminum nitride layer on the second type semiconductor layer; and annealing the aluminum nitride layer to achieve quantum well intermixing.
    Type: Application
    Filed: November 9, 2022
    Publication date: December 14, 2023
    Applicants: National Tsing Hua University, Turning Point Lasers Corporation
    Inventors: Ci-Ling Pan, Chi-Luen Wang, Hung-Sheng Lee, Li-Chang Tsou, Tzu-Neng Lin
  • Publication number: 20230402480
    Abstract: A method of manufacturing a semiconductor device includes disposing a plurality of a first type of light sensing units on a substrate; and disposing a plurality of a second type of light sensing units arranged on the substrate. Each of the first type of light sensing units is operable to receive less radiation than each of the second type of light sensing units. At least one of the second type of light sensing units is adjacent to a portion of at least one of the first type of light sensing units. The method includes disposing a first isolation structure between one of the first type of light sensing units and one of the second type of light sensing units; and disposing a second isolation structure between the adjacent first type of light sensing units. The method includes disposing a reflective layer above the first type of light sensing units.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Li-Wen HUANG, Chung-Lin FANG, Kuan-Ling PAN, Ping-Hao LIN, Kuo-Cheng LEE, Cheng-Ming WU
  • Publication number: 20230207488
    Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 29, 2023
    Inventors: Faxing Che, Hong Wan Ng, Yeow Chon Ong, Wei Yu, Ling Pan, Lin Bu
  • Patent number: 11688662
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments the semiconductor devices include a package substrate, a controller die carried by the package substrate and a spacer carried by the package substrate spaced apart from the controller die. A thermally conductive material can be carried by an upper surface of the controller die and establish a thermal path extending from the upper surface of the controller die to the package substrate. The thermal path can reach the package substrate at a position horizontally between the controller die and the spacer. The semiconductor device can also include one or more dies at least partially carried by the spacer and at least partially above the controller die and the thermally conductive material. Each of the one or more dies is thermally insulated from the thermally conductive material, for example by a thermal adhesive layer between the two.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ling Pan, Sook Har Leong, Kelvin Tan Aik Boo
  • Patent number: 11600754
    Abstract: A light-emitting device (100A) includes: a lead frame (110) including a die paddle (111) and a lead (112) spaced apart from each other; a light-emitting die (120) attached on the die paddle (111); a wire (130) bonding the light-emitting die (120) to the lead (112), wherein a first end (131) of the wire (130) and a region of the light-emitting die (120) to which the first end (131) of the wire (130) is bonded form a first necking area (141); a first resin cover (150a) covering the first necking area (141); and a second resin cover (160) covering the first resin cover (150a), the light-emitting die (120), and the wire (130). The first resin cover (150a) has a hardness lower than a hardness of the second resin cover (160).
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 7, 2023
    Assignee: Lumileds LLC
    Inventors: Hua Sin Yew, Hui Ling Pan, Xinping Yan
  • Publication number: 20230061803
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments the semiconductor devices include a package substrate, a controller die carried by the package substrate and a spacer carried by the package substrate spaced apart from the controller die. A thermally conductive material can be carried by an upper surface of the controller die and establish a thermal path extending from the upper surface of the controller die to the package substrate. The thermal path can reach the package substrate at a position horizontally between the controller die and the spacer. The semiconductor device can also include one or more dies at least partially carried by the spacer and at least partially above the controller die and the thermally conductive material. Each of the one or more dies is thermally insulated from the thermally conductive material, for example by a thermal adhesive layer between the two.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Ling Pan, Sook Har Leong, Kelvin Tan Aik Boo
  • Patent number: D1017796
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: March 12, 2024
    Inventor: Ling Pan
  • Patent number: D1018838
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: March 19, 2024
    Inventor: Ling Pan