Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.

Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.

Abstract: An electronic device and a method for editing a resume are provided. The electronic device includes a display, a transceiver, a storage medium, and a processor. The processor receives personal information through the transceiver, and inputs the personal information into a plurality of item templates to generate an item template with personal information and a blank item template without personal information corresponding to the plurality of item templates. The processor displays the plurality of item templates through the display, and receives a first input operation to add a first item template and a second item template in the plurality of item templates to a resume display area to generate a resume. The processor outputs the resume through the transceiver.

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.

Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.

Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.

Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.

Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a flip chip die electrically coupled to the substrate via a plurality of electrical connections, and a non-conductive film disposed between the flip chip die and the substrate. The non-conductive film may surround the plurality of electrical connections and mechanically couple the flip chip die to the substrate.

Abstract: Substrates having stress-releasing features, and associated systems and methods are disclosed herein. In some embodiments, the substrate includes a core layer, a metallization layer formed on an outer surface of the core layer, and a solder mask formed over the metallization layer and the outer surface. The metallization layer can include at least one bond pad and the solder mask can include a first opening exposing the bond pad. The first opening can be surrounded by a bonding region of the solder mask that thermally interfaces with the bond pad and/or any conductive structure bonded thereon. The solder mask can also include one or more second openings adjacent the first opening. Each of the second openings provides space for the solder mask to expand into to release stress due to thermal expansions of the bond pad, the solder mask, and/or the conductive structure during manufacturing and/or operation.

Abstract: Methods, systems, and devices for connection designs for memory systems are described. A memory system may include a package and a printed circuit board (PCB). An interface of the package may be coupled with the PCB via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the PCB, or both. The memory system may also include a set of latches that may secure the package in a fixed position relative to the PCB. That is, the set of springs may provide an electrical connection between the package and the PCB, and the set of latches may provide a mechanical connection between the package and the PCB. In some examples, the package, the PCB, or both, may include one or more connection structures configured to receive the latches.

Abstract: A method of manufacturing a semiconductor device includes disposing a plurality of a first type of light sensing units on a substrate; and disposing a plurality of a second type of light sensing units arranged on the substrate. Each of the first type of light sensing units is operable to receive less radiation than each of the second type of light sensing units. At least one of the second type of light sensing units is adjacent to a portion of at least one of the first type of light sensing units. The method includes disposing a first isolation structure between one of the first type of light sensing units and one of the second type of light sensing units; and disposing a second isolation structure between the adjacent first type of light sensing units. The method includes disposing a reflective layer above the first type of light sensing units.