Abstract: A work piece holder provided herein includes a support baffle and an elevating element. The support baffle extends along an arc path. The elevating element is disposed on the support baffle and is pivoted to be movable between an unlock status and a lock status.

Abstract: A system for monitoring a wafer carrier includes an overhead hoist transport (OHT) vehicle, a scanner, and a processer. The OHT vehicle is configured to transport the wafer carrier along a vertical direction. The scanner is disposed below the OHT vehicle, wherein the wafer carrier is transported vertically by the OHT vehicle to pass through the scanner, and the scanner at least scans a lower portion of the wafer carrier along a horizontal direction and an upper portion of the wafer carrier along the horizontal direction. The processor is coupled to the scanner, wherein the processer receives a scanning result from the scanner after the wafer carrier is scanned, and the scanning result includes information of a gas composition within the wafer carrier. A method of manufacturing a semiconductor structure including a scanning procedure is also provided.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.

Abstract: Semiconductor device is provided. The semiconductor device includes a first pattern and a second pattern. The first pattern includes a first central part and a plurality of first noncentral parts surrounding the first central part and spaced apart from each other. The second pattern is at a second layer over the first layer of the substrate and at least partially overlapping the first pattern along a first direction passing through the first layer and the second layer. The plurality of first noncentral parts define a vortex arrangement.

Abstract: A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.

Abstract: A method for manufacturing a semiconductor device includes: forming a transistor on a semiconductor substrate, in which the transistor includes a gate structure and a source/drain structure; forming a patterned dielectric layer on the semiconductor substrate, in which the patterned dielectric layer includes an opening extending from a top surface of the patterned dielectric layer to a top surface of the source/drain structure; forming a dielectric contact spacer to cover a sidewall of the opening; and forming a conductive contact in the opening such that the conductive contact is connected to the source/drain structure and is isolated from the gate structure by the dielectric contact spacer and the patterned dielectric layer.

Abstract: A container for receiving a semiconductor device is provided. In one embodiment, the wafer holder assembly includes a first wafer holder with a plurality of first fingers arranged in a first common horizontal plane and a second wafer holder with a plurality of second fingers arranged in a second common horizontal plane. The first wafer holder and the second holder are configured to move relative to each other in a vertical direction, and the first wafer holder and the second holder are configured to rotate relative to each other around a vertical axis.

Abstract: Embodiments of the present disclosure relate to methods for forming a film stack during fabrication or bonding process. The film stack according to present disclosure may reduce wet dip attacking to semiconductor substrate during bonding, such as bonding between an image sensor substrate and a logic device substrate. The film stack according to the present disclosure may be used to modulate stress and wafer warpage to improve bonding adhesion and device performance during various packaging schemes, such as CoWoS, SoIC, or the like. The film stack according to the present disclosure may be used to improve bonding process and device performance in both wafer-to-wafer bonding and die-to-die bonding.

Abstract: A method includes: placing a semiconductor wafer in a chamber during a semiconductor fabrication process; providing a semiconductor cleaning apparatus, the semiconductor cleaning apparatus comprising: a first inlet configured to receive a carrier gas; a gas passageway connected to the first inlet; a second inlet configured to receive one or more fluids; and a fluid passageway connected to the second inlet; delivering the carrier gas from the first inlet to the at least one gas passage branch through the gas passageway; spraying the carrier gas onto the semiconductor wafer; delivering the one or more fluids from the second inlet to the at least one fluid passage branch through the fluid passageway; and spraying the one or more fluids onto the semiconductor wafer.

Abstract: Disclosed are methods of manufacturing semiconductor devices that include the operations of forming an isolation structure in a semiconductor substrate, forming an active region adjacent the isolation structure, forming at least two primary polysilicon structures over the active region, the primary polysilicon structures defining a contacted polysilicon pitch (CPP), and forming a secondary polysilicon structure over the isolation structure. In some methods, the secondary polysilicon structure is further modified and/or replaced in order to provide additional functional elements on the semiconductor devices.

Abstract: A container for receiving a semiconductor device is provided. In one embodiment, the container includes an interior space, a first light reflecting coating in the interior space, a light emitter configured to emit a light from an outside of the interior space into the interior space and toward the first light reflecting coating, and a detector configured to detect the light emitted from the light emitter and reflected by the first light reflecting coating.

Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Abstract: A work piece holder provided herein includes a support baffle and an elevating element. The support baffle extends along an arc path. The elevating clement is disposed on the support baffle and is pivoted to be movable between an unlock status and a lock status.

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

Abstract: A method for forming a semiconductor structure includes following operations. First fins are formed in a first region of a substrate, and second fins are formed in a second region of the substrate. Widths of the first fins are greater than widths of the second fins. An isolation structure is formed over the substrate. A first ion implantation is performed on the first fins. A portion of the isolation structure is removed to expose a portion of each first fin and a portion of each second fin. The widths of the first fins are equal to or less than the widths of the second fins after the removing of the portion of the isolation structure. A 3D capacitor is formed in the first region, and a FinFET device is formed in the second region. The 3D capacitor includes the first fins, and the FinFET device includes the second fins.

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.