Patents by Inventor Ling-Sung Wang
Ling-Sung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220359728Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, Ling-Sung Wang
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Patent number: 11443093Abstract: The semiconductor structure includes first and second active regions arranged in a first grid oriented in a first direction. The semiconductor structure further includes gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction. The first and second active regions are separated, relative to the second direction, by a gap. Each gate electrode includes a first segment and a gate extension. Each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?150 nanometers (nm). Each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular.Type: GrantFiled: August 30, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Chen, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
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Publication number: 20210305386Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.Type: ApplicationFiled: February 12, 2021Publication date: September 30, 2021Inventors: Ru-Shang Hsiao, Ying Hsin Lu, Ching-Hwanq Su, Pin Chia Su, Ling-Sung Wang
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Publication number: 20210305261Abstract: A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut flType: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Patent number: 11037935Abstract: A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.Type: GrantFiled: July 15, 2019Date of Patent: June 15, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
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Publication number: 20210159326Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.Type: ApplicationFiled: May 22, 2020Publication date: May 27, 2021Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, Ling-Sung Wang
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Publication number: 20200203167Abstract: The semiconductor structure includes first and second active regions arranged in a first grid oriented in a first direction. The semiconductor structure further includes gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction. The first and second active regions are separated, relative to the second direction, by a gap. Each gate electrode includes a first segment and a gate extension. Each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?150 nanometers (nm). Each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular.Type: ApplicationFiled: August 30, 2019Publication date: June 25, 2020Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Publication number: 20190341389Abstract: A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Patent number: 10417369Abstract: A semiconductor structure includes: first and second active regions arranged in a first grid oriented in a first direction; and gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction; wherein: the first and second active regions are separated, relative to the second direction, by a gap; each gate electrode includes a first segment and a gate extension; each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?(?150 nm); and each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular. In an embodiment, the height HEXT is HEXT?(?100 nm).Type: GrantFiled: April 10, 2018Date of Patent: September 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Chen, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
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Patent number: 10373962Abstract: A semiconductor device includes: active regions arranged in a first grid oriented parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction. The first gaps are interspersed between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into the corresponding gap.Type: GrantFiled: October 10, 2017Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
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Publication number: 20190019732Abstract: Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: CHAN-YU HUNG, LING-SUNG WANG, YU-JEN CHEN, I-SHAN HUANG
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Patent number: 10181425Abstract: Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width.Type: GrantFiled: July 17, 2017Date of Patent: January 15, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Yu Hung, Ling-Sung Wang, Yu-Jen Chen, I-Shan Huang
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Patent number: 10158004Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.Type: GrantFiled: July 17, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20180342523Abstract: A semiconductor device includes: active regions arranged in a first grid oriented parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction. The first gaps are interspersed between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into the corresponding gap.Type: ApplicationFiled: October 10, 2017Publication date: November 29, 2018Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Publication number: 20180341736Abstract: A semiconductor structure includes: first and second active regions arranged in a first grid oriented in a first direction; and gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction; wherein: the first and second active regions are separated, relative to the second direction, by a gap; each gate electrode includes a first segment and a gate extension; each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?(?150 nm); and each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular. In an embodiment, the height HEXT is HEXT?(?100 nm).Type: ApplicationFiled: April 10, 2018Publication date: November 29, 2018Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
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Patent number: 10090392Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.Type: GrantFiled: January 17, 2014Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: I-Chih Chen, Chih-Mu Huang, Ling-Sung Wang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
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Publication number: 20180261461Abstract: A semiconductor device includes a substrate having a source feature and a drain feature therein configured to enhance charge mobility, a gate stack directly over a portion of the source feature and a portion of the drain feature, a first salicide layer over substantially the entire source feature exposed by the gate stack, and a second salicide layer over substantially the entire drain feature exposed by the gate stack. The first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight. The second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu, Ling-Sung Wang
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Patent number: 10043653Abstract: A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen.Type: GrantFiled: August 27, 2012Date of Patent: August 7, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wei-Cheng Chen, Ling-Sung Wang, Chih-Hsun Lin, Tzu kai Lin
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Patent number: 10008501Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.Type: GrantFiled: September 16, 2016Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
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Patent number: 9978604Abstract: A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.Type: GrantFiled: December 3, 2015Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu, Ling-Sung Wang