Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: The present invention provides an AC power supply capable of programming output impedance and a method for simulating output impedance. The method comprises the following steps. The simulating command, selectively provided by a control circuit, is associated with a voltage adjustment value and a phase adjustment value of a test circuit. The control circuit calculates the voltage adjustment value and a preset voltage value to form a voltage command, and calculates the phase adjustment value and a preset phase value to form a phase command. A power supply circuit generates a simulated output voltage according to the voltage command and the phase command. The preset voltage value and the preset phase value are related to a preset output voltage provided by the power supply circuit, and the simulated output voltage is a simulation of the preset output voltage, provided by the power supply circuit, passed through the test circuit.

Abstract: An optical system includes an objective lens module, an image inverting module, and an eyepiece module. The objective lens module includes a first lens group, a second lens group, a third lens group, a fourth lens group, and a fifth lens group. The optical system satisfies at least one of the following conditions: 0.45?LG4D/LG1D?0.8; 0.015 mm?1?1/fG3?0.045 mm?1; 0.045 mm?1?|1/fG4|?0.07 mm?1; 0.35?|fG4/fG3|?0.75; 0.15?fG1/f?1.6; wherein LG4D is an effective optical diameter of the fourth lens group, LG1D is an effective optical diameter of the first lens group, fG1 is an effective focal length of the first lens group, fG3 is an effective focal length of the third lens group, fG4 is an effective focal length of the fourth lens group, and f is an effective focal length of the objective lens module.

Abstract: In some examples, an electronic device comprises a processor and a power circuit coupled to the processor. The power circuit is to provide power to the processor and to measure a current drawn from the power circuit by the processor. The electronic device also comprises a voltage regulator controller coupled to the processor and the power circuit. The voltage regulator controller is to receive a current usage prediction from the processor, receive the measurement from the power circuit, compare the current usage prediction and the measurement, and, based on the comparison, drive the power circuit in accordance with the measurement instead of the current usage prediction.

Abstract: The present disclosure discloses a digital-analog integrated voltage transformer calibration system, used for calibrating a voltage transformer, the system including: a direct-current high voltage generator, having an input terminal connected with an input terminal of a signal conversion module; the signal conversion module, having an input terminal connected with an output terminal of the voltage transformer and an output terminal connected with a digital quantity acquisition module; the digital quantity acquisition module, having an input terminal connected with the output terminal of the voltage transformer and an output terminal connected with a processing module; the processing module, used for receiving a first digital voltage signal, a second digital voltage signal, and a third digital voltage signal.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: A lighting module includes a lighting unit, a cylindrical optical element, a supporting unit, and a base. The supporting unit connects the base and a part of the supporting unit is higher than a junction of the base and the supporting unit. The lighting unit is disposed on the base and includes a lighting surface emitting a light beam. The cylindrical optical element includes an incident surface and both ends of the cylindrical optical element are respectively connected to the supporting unit making the incident surface facing the lighting surface and having an interval from the lighting unit to the incident surface, and the light beam enters the cylindrical optical element from the incident surface. The lighting module satisfies the following condition: 2?D/E?6; wherein D is a diameter of the cylindrical optical element and E is the interval from the lighting unit to the incident surface.

Abstract: Examples herein relate to ambient noise level detection. For instance, in some examples an electronic device includes a cooling resource and a processor resource to alter an operational speed of the cooling resource from an initial operational speed to a first altered operational speed, detect an ambient noise level, compare the ambient noise level to a first noise threshold, and restrict the operational speed of the cooling resource to be less than the initial operational speed.

Abstract: In some examples, an electronic device comprises a processor and a power circuit coupled to the processor. The power circuit is to provide power to the processor and to measure a current drawn from the power circuit by the processor. The electronic device also comprises a voltage regulator controller coupled to the processor and the power circuit. The voltage regulator controller is to receive a current usage prediction from the processor, receive the measurement from the power circuit, compare the current usage prediction and the measurement, and, based on the comparison, drive the power circuit in accordance with the measurement instead of the current usage prediction.

Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

Abstract: An optical device and the prism module thereof are provided. The prism module includes a first prism, a second prism, and a third prism. The second prism is disposed beside the first prism. The third prism is adhered to the second prism. First light enters the first prism, is reflected plural times in the first prism, enters the second prism, and is emitted from the second prism. Second light enters the second prism, is reflected plural times in the second prism, and is emitted from the second prism. Third light sequentially passes through the third prism and the second prism, enters the first prism, is reflected plural times in the first prism, and is emitted from the first prism.

Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion with a first sidewall and a second portion with a second sidewall, and the first sidewall and the second sidewall have different slopes. The package structure also includes a semiconductor chip beside the conductive structure and a protective layer laterally surrounding the conductive structure and the semiconductor chip. The protective layer covers the first sidewall of the first portion and the second sidewall of the second portion. The protective layer is made of a polymer material dispersed with fillers.

Abstract: The present disclosure provides an electronic document processing method and apparatus, a terminal and a storage medium. The electronic document processing method comprises: in response to a first operation on target content of an electronic document, determining a target content block; and according to the first operation and the content type of the target content block, displaying at least one associated operation option, wherein the content block is a unit used for carrying the content of the electronic document, and the operation option is configured to use the content block as an operation object; and in response to a triggering operation on a target operation option, performing an operation on the target content block according to the target operation option.

Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

Abstract: An optical device and the prism module thereof are provided. The prism module includes a first prism, a second prism, and a third prism. The second prism is disposed beside the first prism. The third prism is adhered to the second prism. First light enters the first prism, is reflected plural times in the first prism, enters the second prism, and is emitted from the second prism. Second light enters the second prism, is reflected plural times in the second prism, and is emitted from the second prism. Third light sequentially passes through the third prism and the second prism, enters the first prism, is reflected plural times in the first prism, and is emitted from the first prism.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: An example computing device includes a plurality of interfaces to connect to a plurality of audio peripheral devices, a communications interface to establish a network connection, and a processor interconnected with the plurality of interfaces and the communications interface. The processor is to determine a location of the computing device based on the network connection. The processor sets an audio peripheral device from the plurality of the audio peripheral devices as a default audio peripheral device based on the location. The processor communicates an audio signal through the default audio peripheral device.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.