Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Abstract: A package structure includes a first semiconductor die having a first conductive pad and a second semiconductor die having a second conductive pad. The package structure also includes a conductive structure and a third semiconductor die. The third semiconductor die extends across a portions of the first semiconductor die and the second semiconductor die. A third conductive pad and a fourth conductive pad of the third semiconductor die are aligned with the first conductive pad and the second conductive pad, respectively. The package structure further includes a protective layer surrounding the conductive structure and the third semiconductor die and an insulating layer extending across an interface between the protective layer and the conductive structure. The package structure includes a conductive layer electrically connected to the conductive structure. The conductive layer has a first portion spaced from the conductive structure and a second portion directly above the conductive structure.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor die. The method further includes forming an insulating layer over the protective layer. The insulating layer has an opening exposing a portion of the conductive structure. In addition, the method includes forming a conductive layer over the insulating layer. The conductive layer fills the opening, and the conductive layer has a substantially planar top surface.

Abstract: An optical system includes an objective lens module, an image inverting module, and an eyepiece module. The objective lens module includes a first lens group, a second lens group, a third lens group, a fourth lens group, and a fifth lens group. The optical system satisfies at least one of the following conditions: 0.45?LG4D/LG1D?0.8; 0.015 mm?1?1/fG3?0.045 mm?1; 0.045 mm?1?|1/fG4|?0.07 mm?1; 0.35?|fG4/fG3|?0.75; 0.15?fG1/f?1.6; wherein LG4D is an effective optical diameter of the fourth lens group, LG1D is an effective optical diameter of the first lens group, fG1 is an effective focal length of the first lens group, fG3 is an effective focal length of the third lens group, fG4 is an effective focal length of the fourth lens group, and f is an effective focal length of the objective lens module.

Abstract: In some examples, an electronic device comprises a processor and a power circuit coupled to the processor. The power circuit is to provide power to the processor and to measure a current drawn from the power circuit by the processor. The electronic device also comprises a voltage regulator controller coupled to the processor and the power circuit. The voltage regulator controller is to receive a current usage prediction from the processor, receive the measurement from the power circuit, compare the current usage prediction and the measurement, and, based on the comparison, drive the power circuit in accordance with the measurement instead of the current usage prediction.

Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Abstract: The present disclosure is applicable to the technical field of metering and distributing of an adhesive dispensing machine, and provides a machine learning-based flexible intelligent adhesive dispensing method.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

Abstract: In one embodiment, a method comprises determining, by a controller device in a low power and lossy network (LLN), that a first LLN border device is in a first personal area network (PAN) having a first directed acyclic graph (DAG) topology, and that the first LLN border device is a neighbor of a second LLN border device in a second PAN of the LLN having a second DAG topology; receiving a path request for a third LLN device in the first PAN to reach a fourth LLN device in the second PAN; and generating an inter-PAN path between the third LLN device and the fourth LLN device via the first and second LLN border devices, the inter-PAN path providing a stitching between the first DAG topology and the second DAG topology.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Abstract: An example computing device includes a plurality of interfaces to connect to a plurality of audio peripheral devices, a communications interface to establish a network connection, and a processor interconnected with the plurality of interfaces and the communications interface. The processor is to determine a location of the computing device based on the network connection. The processor sets an audio peripheral device from the plurality of the audio peripheral devices as a default audio peripheral device based on the location. The processor communicates an audio signal through the default audio peripheral device.

Abstract: In one embodiment, a method comprises: determining, by a network device that is configured for joining a local directed acyclic graph (DAG) instance in a data network, an unreachability by the network device to any member of the local DAG instance; generating and broadcasting, by the network device, a request message that identifies the network device requesting to join the local DAG instance, the request message causing a neighboring network device in a global DAG instance of the data network to rebroadcast the request message for reception by a member of the local DAG instance, the neighboring network device a non-member of the local DAG instance; and receiving, by the network device, a reply message indicating a member of the local DAG instance is reachable via the neighboring network device in the global DAG instance.

Abstract: In one embodiment, a method comprises determining, by a controller device in a low power and lossy network (LLN), that a first LLN border device is in a first personal area network (PAN) having a first directed acyclic graph (DAG) topology, and that the first LLN border device is a neighbor of a second LLN border device in a second PAN of the LLN having a second DAG topology; receiving a path request for a third LLN device in the first PAN to reach a fourth LLN device in the second PAN; and generating an inter-PAN path between the third LLN device and the fourth LLN device via the first and second LLN border devices, the inter-PAN path providing a stitching between the first DAG topology and the second DAG topology.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.

Abstract: In one embodiment, a method comprises: determining, by a network device that is configured for joining a local directed acyclic graph (DAG) instance in a data network, an unreachability by the network device to any member of the local DAG instance; generating and broadcasting, by the network device, a request message that identifies the network device requesting to join the local DAG instance, the request message causing a neighboring network device in a global DAG instance of the data network to rebroadcast the request message for reception by a member of the local DAG instance, the neighboring network device a non-member of the local DAG instance; and receiving, by the network device, a reply message indicating a member of the local DAG instance is reachable via the neighboring network device in the global DAG instance.

Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.