Patents by Inventor Ling Wu

Ling Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11944746
    Abstract: A fluid delivery apparatus comprises a first piston body, a second piston body, a fluid delivery pipe, and a sealing element. The first piston body has a first through hole, a first connecting portion, an accommodation space and a buffer space. The second piston body has a second through hole and a second connecting portion disposed inside the accommodation space. The fluid delivery pipe is accommodated in the first through hole and the second through hole, and movable between a first position and a second position. The sealing element encircles the fluid delivery pipe. When the fluid delivery pipe is at the first position, the sealing element is accommodated in the accommodation space. When the fluid delivery pipe is at the second position, a first part of the sealing element is accommodated in the accommodation space, and a second part of the sealing element is accommodated in the buffer space.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: April 2, 2024
    Assignee: MICROBASE TECHNOLOGY CORP.
    Inventors: Chiu-Ju Shen, Po Chuan Chen, Jo Ling Wu
  • Patent number: 11947473
    Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 2, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Haikun Dong, Kostantinos Danny Christidis, Ling-Ling Wang, MinHua Wu, Gaojian Cong, Rui Wang
  • Patent number: 11947092
    Abstract: A lens assembly includes a first lens group, a second lens group, a third lens group, a fourth lens group, a fifth lens group, a sixth lens group, and a first reflective element. The first and third lens groups are with negative refractive power. The second and fourth lens groups are with positive refractive power. The fifth and sixth lens groups are with refractive power. The first, second, third, fourth, fifth, and sixth lens groups are arranged in order from a first side to a second side along an axis. The first reflective element includes a first reflective surface. A light from the first side sequentially passes through the first, second, third, fourth, fifth, and sixth lens groups to the second side. The first reflective element is disposed between the first lens group and the sixth lens group.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: April 2, 2024
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventors: Hsi-Ling Chang, Guo-Yang Wu
  • Publication number: 20240100193
    Abstract: Provided herein are recombinant self-complementary adeno-associated virus (scAAV) nucleic acid vectors that comprise a ubiquitous eukaryotic promoter, such as elongation factor 1? (EF1?), chicken beta-actin (CBA), and hybrid chicken beta-actin (CBh), followed by a dominant negative RhoA. Also provided herein are methods of use of said vectors, including intraocular injections (e.g., intracameral injections) to reduce intra-ocular pressure (TOP). Also provided herein are plasmids, recombinant scAAV particles, compositions, formulations, and other methods of use related to such vectors.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 28, 2024
    Inventors: Terete Borras, Guiying Hong, Bo Liang, Ling Wu, Carola Maturana
  • Publication number: 20240104594
    Abstract: Participation by multiple users in an online game through client computing platforms associated with the users is facilitated. User accounts associated with the users indicate affiliations having a functional significance between users. Presentation of offers to sell virtual items are provided to users having a first affiliation and to users having a second affiliation. The virtual items associated with the offers are distributed to the users having a first affiliation upon an indication that a threshold number of users having the first affiliation have accepted the offer and are not distributed to users having a second affiliation upon an indication that a threshold number of users having the second affiliation have not accepted the offer.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: John Kim, Kevin Lee, Kevin Chanthasiriphan, Wei-Ling Wu Deckinga, Tomi Huttula
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11933969
    Abstract: An optical engine module including at least two laser sources, collimators, a light combining lens group, an aperture, a beam shaping lens group, a MEMS scanning module, and a beam expansion lens group is provided. The at least two laser sources respectively generate at least two laser beams with different wavelengths. The collimators respectively collimate the at least two laser beams to generate at least two collimated beams. The light combining lens group combines the at least two collimated beams into a combined beam. The aperture filters stray beams of the combined beam. The beam shaping lens group shapes the combined beam to generate a shaped beam with a perfect circle. The MEMS scanning module reflects the shaped beam and scans in horizontal and vertical directions to form a scanning beam. The beam expansion lens group expands the scanning beam into an expanded beam having a predetermined area.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: March 19, 2024
    Assignee: MEGA1 COMPANY LTD.
    Inventors: Makoto Masuda, Han-Chiang Wu, Shan-Ling Yeh, Tzu-Chieh Lien
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Publication number: 20240088208
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: Tzu-Ting LIU, Hsiang-Ku SHEN, Wen-Tzu CHEN, Man-Yun WU, Wen-Ling CHANG, Dian-Hau CHEN
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240087988
    Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
  • Publication number: 20240087980
    Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
  • Patent number: 11929851
    Abstract: A gateway device selection method is provided. The method includes: receiving, by a terminal device, a message from a gateway device, where the message includes identification information of the gateway device, and the identification information of the gateway device indicates information about the gateway device; determining, by the terminal device, that the identification information of the gateway device is consistent with preset identification information of a gateway device on the terminal device, and using the gateway device as a selected gateway device; and sending, by the terminal device, a data packet to the selected gateway device. This helps the terminal device correctly identify the gateway device to which the terminal device is to send data.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 12, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yun Qin, Ling Wu
  • Publication number: 20240077188
    Abstract: A light source module includes a first light source and a second light source. The first light source is configured for emitting a first light having a first wavelength, and the first light includes a first part and a second part. The second light source is configured for emitting a second light having a second wavelength. The second light source includes a first wavelength conversion layer, and the first wavelength conversion layer is configured for converting the first light into the second light. One of the first part and the second part is incident to the first wavelength conversion layer, and the other of the first part and the second part is not incident to the first wavelength conversion layer.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 7, 2024
    Applicant: Qisda Corporation
    Inventors: Chih-Shiung CHIEN, Ming-Kuen LIN, Tsung-Hsun WU, Yi-Ling LO
  • Publication number: 20240067591
    Abstract: Disclosed in the present disclosure are a method and system for producing hexafluoro-1,3-butadiene. It includes: under the action of a catalyst, chlorotrifluoroethylene reacting with hydrogen gas in a first reactor to obtain a mixture, the mixture entering a rectification apparatus, trifluoroethylene obtained by rectification entering a second reactor and reacting with bromine under light to obtain 1,2-dibromo-trifluoroethane; in a third reactor pre-loaded with the 1,2-dibromo-trifluoroethane, adding the 1,2-dibromo-trifluoroethane and solid alkali, and performing reaction to obtain bromotrifluoroethylene; and adding the bromotrifluoroethylene to a fourth reactor holding with zinc powder, an initiator and an organic solvent for reaction, so as to obtain a trifluoroethenyl zinc bromide solution, performing filtration, and then adding a coupling agent for a coupling reaction, so as to obtain hexafluoro-1,3-butadiene.
    Type: Application
    Filed: February 27, 2023
    Publication date: February 29, 2024
    Inventors: Wucan LIU, Haifeng WU, Ling LI, Hao CHENG, Jingtian ZHANG, Jiexun CHEN
  • Publication number: 20240071451
    Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
    Type: Application
    Filed: January 21, 2021
    Publication date: February 29, 2024
    Inventors: Huai LIN, Guozhong XING, Zuheng WU, Long LIU, Di WANG, Cheng LU, Peiwen ZHANG, Changqing XIE, Ling LI, Ming LIU
  • Patent number: 11912793
    Abstract: A polypeptide and an application thereof in bone repair are provided. An amino acid sequence of the polypeptide provided by the invention is shown as SEQ ID NO: 1. The invention further discloses use of the polypeptide GS18 in bone injury and/or bone repair. Furthermore, the invention further discloses an application of the polypeptide GS18 as well as a polypeptide scaffold for bone repair. The polypeptide of the invention demonstrates the ability to translocate ?-catenin into the nucleus and induce the expression of secreted protein osteocalcin in vivo. In vitro, the polypeptide facilitates the osteogenic differentiation of osteogenesis-oriented BMSCs (pre-osteoblasts thereby promoting the process of bone repair.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: February 27, 2024
    Assignee: SICHUAN UNIVERSITY
    Inventors: Ling Ye, Fanyuan Yu, Jiayi Wu, Feifei Li
  • Patent number: 11916017
    Abstract: An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ling Chang, Chih-Liang Chen, Chia-Tien Wu, Guo-Huei Wu
  • Patent number: 11901228
    Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
  • Patent number: 11901618
    Abstract: An electronic device is provided. The electronic device includes a first substrate, a multilayer structure, and a passivation layer. The multilayer structure is disposed on the first substrate. The multilayer structure includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The passivation layer is disposed on the second conductive layer. In addition, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the passivation layer.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: February 13, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Ping Tseng, Ker-Yih Kao, Chia-Chi Ho, Ming-Yen Weng, Hung-I Tseng, Shu-Ling Wu, Huei-Ying Chen