Abstract: A method of manufacturing a semiconductor device includes providing a first layer over a wafer substrate, providing a polysilicon layer over the first layer, implanting nitrogen ions into the polysilicon layer, forming a polycide layer over the polysilicon layer, and forming source and drain regions.

Abstract: A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region.

Abstract: An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.

Abstract: A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.

Abstract: An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO) layer is formed on the to-be-etched substrate. Afterwards, an anti-reflective layer is formed on the SRO layer. Then, a patterned photo resist layer is formed on the anti-reflective layer. Afterwards, the anti-reflective layer, the SRO layer and the to-be-etched substrate is etched so as to form an opening.

Abstract: The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.

Abstract: A fabrication method of an electronic device is provided. First, a substrate is provided. Then, a patterned amorphous carbon (?-C) layer is formed on the substrate and exposes part of the substrate. Next, a first ?-C layer covering the patterned ?-C layer and part of the substrate is formed. Then, part of the substrate and part of the first ?-C layer covering part of the substrate are removed, so as to form a patterned substrate and a second ?-C layer.

Abstract: Semiconductor structures and methods of fabricating semiconductor structures are disclosed. The method comprises the steps of: providing an initial semiconductor structure; forming a non-silicon layer overlying the initial semiconductor structure, the non-silicon layer having an extinction coefficient greater than zero at wavelengths below about 300 nanometers; and performing a plasma-based process to form a layer overlying the non-silicon layer, the non-silicon layer preventing the ultraviolet radiation generated during the plasma-based process from damaging the initial semiconductor structure.

Abstract: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form a trench. An oxide liner and a nitride liner are then formed in the trench. Subsequently, a two-stage high-density plasma chemical vapor deposition process is performed to form a shallow trench isolation region.

Abstract: A semiconductor device with an unlanded via having an air gap dielectric layer and a silicon-rich oxide (SRO) inter-metal dielectric (IMD) layer, and a method of making the same are provided. The SRO layer acts as an etch-stop layer to prevent unlanded via penetration completely through the IMD layer. In addition, the SRO has a higher extinction coefficient (k) than conventional high-density plasma (HDP) oxide layers, thereby preventing plasma etch damage and excessive void formation in an unlanded via.

Abstract: A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.

Abstract: The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.

Abstract: A nitride read only memory comprises a selectively grown, epitaxial, shunt silicon layer (shunt layer) that reduces the bit line sheet resistance and increases bit line mobility. The shunt layer can be grown by a in situ, P-doped deposit at high temperature. A bit line interface without native oxide and excellent electron mobility can be achieved using the methods for selective epitaxial growth described herein.

Abstract: A novel cleaning method for preventing defects and particles resulting from post tungsten etch back or tungsten chemical mechanical polish is provided. The cleaning method comprises providing a stack structure of a semiconductor device including a tungsten plug in a dielectric layer. The tungsten plug has a top excess portion. A surface of the stack structure is then contacted with a cleaning solution comprising hydrogen peroxide. Next, the surface of the stack structure is contacted with dilute hydrofluoric acid. The cleaning solution and hydrofluoric acid are capable of removing the top excess portion and particles on the surface of the stack structure.

Abstract: A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration key overlay shift can be improved.

Abstract: A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer by remote plasma nitrogen (RPN).

Abstract: A method of manufacturing a semiconductor device includes providing a first layer over a wafer substrate, providing a polysilicon layer over the first layer, implanting nitrogen ions into the polysilicon layer, forming a polycide layer over the polysilicon layer, and forming source and drain regions.

Abstract: A method of forming a semiconductor device that includes providing a semiconductor substrate, forming a first insulating layer over the semiconductor substrate, forming a floating gate over the first insulating layer with a reaction gas, wherein the floating gate comprises a microcrystalline material having a grain size of about 50–300 ?, forming a second insulating layer over the floating gate, and forming a control gate over the second insulating layer.

Abstract: In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.

Abstract: A method of forming a semiconductor device that includes providing a semiconductor substrate, forming a first insulating layer over the semiconductor substrate, forming a floating gate over the first insulating layer with a reaction gas, wherein the floating gate comprises a microcrystalline material having a grain size of about 50-300 ?, forming a second insulating layer over the floating gate, and forming a control gate over the second insulating layer.