Abstract: Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, a first sidewall spacer on a sidewall of the gate structure, a first diffusion region in the substrate and adjacent to the gate structure, the first sidewall spacer and the first diffusion region being on one side of the gate structure, and a first conductive layer in the first diffusion region, the first conductive layer being spaced apart from the first sidewall spacer.

Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

Abstract: Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.

Abstract: Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.

Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

Abstract: An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

Abstract: A protection circuit for a CMOS integrated circuit which is biased with a first voltage and a second voltage includes a voltage divider, a voltage comparator, and a switch. The full level of the first voltage is higher than that of the second voltage. The voltage divider divides the first voltage to be compared with the second voltage in the voltage comparator. The switch is controlled by the voltage comparator. The switch isolates the CMOS integrated circuit from the first voltage when the first voltage is lower than the second voltage. Therefore, no forward bias current path exists in the CMOS integrated circuit even though the voltage levels of the first and second voltages reach their full levels at different times.