Abstract: A high-bandwidth memory (HBM) device with localized refresh adjustment is disclosed. The HBM device contains one or more volatile memory dies, each with memory arrays and associated temperature sensors which characterize the temperature of the memory arrays. A refresh management circuit of the HBM device receives refresh commands directed to a certain memory array, determines the temperature of the array, and performs one or more refresh operations based on the temperature of the memory array or a portion thereof. The refresh commands may come from a host device coupled to the HBM device and/or be generated by the HBM device.

Abstract: A stacked memory device (e.g., a high-bandwidth memory (HBM) device) having a storage component is disclosed. The stacked memory device can include a first logic die, one or more memory dies, a second logic die, and one or more storage dies. The first logic die is coupled with the one or more memory dies and the second logic die through TSVs. The second logic die is coupled with the one or more storage dies through additional TSVs. The first logic die can issue commands to the one or more memory dies that cause the one or more memory dies to perform operations (e.g., read/write operations). The first logic die can also issue commands to the second logic die that cause the second logic die to issue commands to the one or more storage dies to perform operations.

Abstract: An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The apparatus may include multiple HBM cubes connected to a processor, such as a GPU. The HBM cubes may be connected in series or in parallel. One or more of the HBM cubes can include a secondary communication circuit configured to facilitate the expanded connection between the multiple cubes.

Abstract: An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.

Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.

Abstract: Methods, apparatuses, and systems related to a memory controller on an interface die and outside of a processor are described. Operations of the memory controller may be further facilitated by a circuit interface fabric configured to utilize separate write and read data buses within the interface die.

Abstract: Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.

Abstract: System-in-packages (SiPs) having vertically integrated processing units and combined high-bandwidth memory (HBM) devices, and associated devices and methods, are disclosed herein. In some embodiments, the SiP includes a processing unit and a HBM device carried by the processing unit. Further, the combined HBM device can include one or more volatile memory dies and one or more non-volatile memory dies. The SiP can also include a shared through silicon via (TSV) bus that electrically couples combined HBM device can also include a shared bus that is electrically coupled to each of the processing unit, the one or more volatile memory dies, and the one or more non-volatile memory dies to establish communication paths therebetween.

Abstract: An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.

Abstract: Heterogeneous integrated circuits with voltage booster circuits (e.g., inductor-based pumps) and associated systems and methods, are disclosed herein. In one embodiment, a heterogeneous integrated circuit includes (a) one or more first dies of a first type and (b) a second die of a second type different from the first type. The first die(s) can be integrated with (e.g., stacked on, bonded to, interconnected with) the second die. The heterogeneous integrated circuit can further include a voltage booster circuit, such as an inductor-based pump. The inductor-based pump can (i) include an inductor positioned within the second die, (ii) include an input configured to receive a first voltage, and (iii) include an output coupled to the first die(s). The inductor-based pump can be configured to (a) boost the first voltage to a second voltage greater than the first voltage and (b) output the second voltage at the output.

Abstract: System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and a heat-mitigating high-bandwidth memory (HBM) device each integrated with the base substrate. The heat-mitigating HBM device can include a stack of one or more memory dies and an interface die carried by the stack of one or more memory dies. The interface die includes an input/output (IO) circuit that is accessible through an upper surface of the interface die. The SiP device can also include a communication substrate carried by the host device and the heat-mitigating HBM device, as well as a thermal interface material carried by the communication substrate. The communication substrate can include one or more communication channels communicably coupling the IO circuit of the interface die to the host device.

Abstract: Systems and methods are provided for using a 2.5D PHY and a 3D PHY for communications between a memory device and a host device. The memory device includes a 2.5D PHY for communications with the host device through a predefined communication interface and a 3D PHY for communications with the host device through a customized communication interface. The 2.5D PHY of the memory device is used for communications through the predefined communication interface when the customized communication interface is not available or undesired (e.g., during testing of the memory device).

Abstract: System-in-packages (SiPs) having hybrid high bandwidth memory (HBM) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP includes a base substrate, as well as a processing device and a hybrid high-bandwidth memory (HBM) device each carried by the base substrate. The processing device includes a processing unit and a first cache memory associated with a first level of a cache hierarchy. The hybrid HBM device is electrically coupled to the processing unit through a SiP bus in the base substrate. Further, the hybrid HBM device includes an interface die, one or more memory dies carried by the interface die, and a shared bus electrically coupled to the interface die and each of the memory dies. The hybrid HBM device also includes a second cache memory formed on the interface die that is associated with a second level of the cache hierarchy.

Abstract: System-in-package (SiP) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP devices include a base substrate, as well as a processing unit a high bandwidth memory (HBM) device, and a high bandwidth storage (HBS) device each carried by the base substrate. The HBM device is electrically coupled to the processing unit through a SiP bus and includes a first interface die, one or more volatile memory dies, and an HBM bus electrically coupled to the first interface die and each of the one or more volatile memory dies. The HBS device is electrically coupled to the HBM device through the SiP bus and includes a second interface die one or more non-volatile memory dies, and an HBS bus electrically coupled to the second interface die and each of the one or more non-volatile memory dies.

Abstract: System-in-package (SiP) having functional high bandwidth memory (HBM) devices, and associated systems and methods are disclosed herein. In some embodiments, the functional HBM devices can include a controller die, one or more volatile memory dies, a flash memory die, and an HBM bus communicably coupled to each of the controller, volatile memory, and flash memory dies. The flash memory die can include one or more word lines that each have multiple programmable memory cells, as well as multiple bit lines. Each of the bit lines is coupled to a corresponding programmable memory cell from each of the one or more word lines. During operation, the controller die is configured to control the volatile memory dies and the flash memory die, through a shared bus therebetween, to implement one or more neural network computing operations within the functional HBM device.

Abstract: An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.

Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

Abstract: High-bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the HBM devices include a first die (e.g., an interface die), a plurality of second dies (e.g., memory dies) carried by the first die communicably coupled to the first die through a plurality of HBM bus through substrate vias (TSVs). The HBM devices also include an HBM testing component carried at least partially by an upper surface of an uppermost second die. The HBM testing component provides access to the first and second dies through an uppermost surface of the HBM device to test the HBM device during manufacturing. For example, the HBM testing component allows the first and second dies to be tested after the HBM device is mounted to a base substrate of a system-in-package without requiring any footprint for access pins on the base substrate.

Abstract: A stacked memory device (e.g., a high-bandwidth memory (HBM) device) having a storage component is disclosed. The stacked memory device can include a first logic die, one or more memory dies, a second logic die, and one or more storage dies. The first logic die is coupled with the one or more memory dies and the second logic die through TSVs. The second logic die is coupled with the one or more storage dies through additional TSVs. The first logic die can issue commands to the one or more memory dies that cause the one or more memory dies to perform operations (e.g., read/write operations). The first logic die can also issue commands to the second logic die that cause the second logic die to issue commands to the one or more storage dies to perform operations.

Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.