Patents by Inventor Lingming Yang
Lingming Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942139Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.Type: GrantFiled: December 6, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Lingming Yang, Nevil N. Gajera, John Christopher M. Sancon
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Publication number: 20240004756Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.Type: ApplicationFiled: June 20, 2023Publication date: January 4, 2024Inventors: Joseph M. McCrate, Marco Sforzin, Paolo Amato, Lingming Yang, Nevil N. Gajera
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Patent number: 11782830Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: GrantFiled: December 20, 2021Date of Patent: October 10, 2023Assignee: Micron Technologies, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Patent number: 11775431Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: GrantFiled: December 20, 2021Date of Patent: October 3, 2023Assignee: Micron Technologies, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20230267996Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera, Amitava Majumdar
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Publication number: 20230236931Abstract: Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.Type: ApplicationFiled: August 24, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala, Nevil Gajera
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Publication number: 20230236933Abstract: Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.Type: ApplicationFiled: January 18, 2023Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Sandeep Krishna THIRUMALA, Lingming YANG, Amitava MAJUMDAR, Nevil GAJERA
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Publication number: 20230238049Abstract: Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.Type: ApplicationFiled: June 20, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Sandeep Krishna Thirumala, Amitava Majumdar, Lingming Yang, Nevil Gajera
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Publication number: 20230236934Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.Type: ApplicationFiled: August 24, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala, Nevil Gajera
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Patent number: 11694747Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.Type: GrantFiled: June 3, 2021Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera, Amitava Majumdar
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Publication number: 20230195624Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20230195623Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Patent number: 11664074Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.Type: GrantFiled: June 2, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, Yen Chun Lee, Jessica Chen, Francesco Douglas Verna-Ketel
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Publication number: 20230102468Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Inventors: Karthik Sarpatwari, Lingming Yang, Nevil N. Gajera, John Christopher M. Sancon
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Patent number: 11616098Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.Type: GrantFiled: June 6, 2022Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Lingming Yang, Karthik Sarpatwari, Fabio Pellizzer, Nevil N. Gajera, Lei Wei
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Patent number: 11587614Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.Type: GrantFiled: August 5, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Josephine Tiu Hamada, Kenneth Richard Surdyk, Lingming Yang, Mingdong Cui
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Publication number: 20230048450Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.Type: ApplicationFiled: November 3, 2022Publication date: February 16, 2023Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, John F. Schreck
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Patent number: 11545194Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.Type: GrantFiled: May 3, 2021Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Nevil N. Gajera, Jessica Chen, Lingming Yang
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Patent number: 11532347Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.Type: GrantFiled: February 4, 2021Date of Patent: December 20, 2022Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Lingming Yang, Nevil N. Gajera, John Christopher M. Sancon
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Patent number: 11527287Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.Type: GrantFiled: May 27, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, John F. Schreck