Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

Abstract: The present invention relates to the technical field of memories, and in particular to a highly-consistent resistive memory and method of fabricating the same. The resistive memory comprises: a lower electrode which is formed in a first dielectric layer by patterning; a second dielectric layer formed on the lower electrode and the first dielectric layer and provided with an opening for exposing the lower electrode to perform patterning; an edge wall formed in the opening of the second dielectric layer for covering a border area of the lower electrode and the first dielectric layer so that only the middle area of the lower electrode is partially or totally exposed; a storage medium layer formed by performing oxidization with the second dielectric layer and the edge wall as mask; and an upper electrode. The resistive memory exhibits good consistency and high reliability; moreover, unit size is mall, which is advantageous for improving storage characteristic.

Abstract: The present invention relates to the technical field of memories, and in particular to a highly-consistent resistive memory and method of fabricating the same. The resistive memory comprises: a lower electrode which is formed in a first dielectric layer by patterning; a second dielectric layer formed on the lower electrode and the first dielectric layer and provided with an opening for exposing the lower electrode to perform patterning; an edge wall formed in the opening of the second dielectric layer for covering a border area of the lower electrode and the first dielectric layer so that only the middle area of the lower electrode is partially or totally exposed; a storage medium layer formed by performing oxidization with the second dielectric layer and the edge wall as mask; and an upper electrode. The resistive memory exhibits good consistency and high reliability; moreover, unit size is mall, which is advantageous for improving storage characteristic.