Patents by Inventor Lingpeng Guan

Lingpeng Guan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11869967
    Abstract: An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: January 9, 2024
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Sik Lui, Madhur Bobde, Lingpeng Guan, Lei Zhang
  • Patent number: 11774296
    Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: October 3, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Zhenyu Wang, Jian Yin, Lingpeng Guan, Sitthipong Angkititrakul, Christopher Ben Bartholomeusz, Xiaobin Wang
  • Patent number: 11756993
    Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: September 12, 2023
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Bum-Seok Suh
  • Patent number: 11749716
    Abstract: A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile includes multiple doped regions with peak doping levels where a first doped region adjacent to a first side of the field stop zone has a first peak doping level that is not higher than a last peak doping level of a last doped region adjacent to the base region. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 5, 2023
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Lei Zhang, Karthik Padmanabhan, Lingpeng Guan, Jian Wang, Lingbing Chen, Wim Aarts, Hongyong Xue, Wenjun Li, Madhur Bobde
  • Patent number: 11728423
    Abstract: Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: August 15, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Wenjun Li, Lingpeng Guan, Jian Wang, Lingbing Chen
  • Publication number: 20230147081
    Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Inventors: Zhenyu Wang, Jian Yin, Lingpeng Guan, Sitthipong Angkititrakul, Christopher Ben Bartholomeusz, Xiaobin Wang
  • Patent number: 11594613
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: June 13, 2021
    Date of Patent: February 28, 2023
    Assignee: Alpha and Omega Semiconductor, Ltd.
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20230049581
    Abstract: An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Inventors: Sik Lui, Madhur Bobde, Lingpeng Guan, Lei Zhang
  • Patent number: 11569345
    Abstract: A method for manufacturing and a Super Junction MOSFET are disclosed. The Super Junction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type. A deep trench is formed in the epitaxial layer. The deep trench having an insulating layer with a thickness gradient formed on surfaces of the deep trench. One or more regions of the epitaxial layer proximate to sidewalls of the deep trench is doped of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type. Finally, MOSFET device structures are formed in the epitaxial layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: January 31, 2023
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Wenjun Li, Lingbing Chen, Lingpeng Guan, Jian Wang
  • Patent number: 11508819
    Abstract: A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 22, 2022
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Publication number: 20220344505
    Abstract: Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Inventors: Wenjun Li, Lingpeng Guan, Jian Wang, Lingbing Chen
  • Publication number: 20220262898
    Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Bum-Seok Suh
  • Publication number: 20220165843
    Abstract: A method for manufacturing and a Super Junction MOSFET are disclosed. The Super Junction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type. A deep trench is formed in the epitaxial layer. The deep trench having an insulating layer with a thickness gradient formed on surfaces of the deep trench. One or more regions of the epitaxial layer proximate to sidewalls of the deep trench is doped of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type. Finally, MOSFET device structures are formed in the epitaxial layer.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 26, 2022
    Inventors: Wenjun Li, Lingbing Chen, Lingpeng Guan, Jian Wang
  • Patent number: 11342410
    Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 24, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Bum-Seok Suh
  • Publication number: 20210305406
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Application
    Filed: June 13, 2021
    Publication date: September 30, 2021
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20210273046
    Abstract: A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile includes multiple doped regions with peak doping levels where a first doped region adjacent to a first side of the field stop zone has a first peak doping level that is not higher than a last peak doping level of a last doped region adjacent to the base region. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.
    Type: Application
    Filed: May 4, 2021
    Publication date: September 2, 2021
    Inventors: Lei Zhang, Karthik Padmanabhan, Lingpeng Guan, Jian Wang, Lingbing Chen, Wim Aarts, Hongyong Xue, Wenjun Li, Madhur Bobde
  • Patent number: 11101137
    Abstract: A process is applied to develop a plurality of reverse conducting insulated gate bipolar transistors (RCIGBTs). The process comprises the steps of providing a wafer, applying a first grinding process, patterning a mask, applying an etching process, removing the mask, implanting N++ type dopant, applying a second grinding process forming a TAIKO ring, implanting P+ type dopant, annealing and depositing TiNiAg or TiNiVAg, removing the TAIKO ring, attaching a tape, and applying a singulation process. The mask can be a soft mask or a hard mask. The etching process can be a wet etching only; a wet etching followed by a dry etching; or a dry etching only.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 24, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Zhiqiang Niu, Long-Ching Wang, Yueh-Se Ho, Lingpeng Guan, Wenjun Li
  • Publication number: 20210257461
    Abstract: A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Patent number: 11038037
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 11038022
    Abstract: A superjunction power semiconductor device includes a termination region with superjunction structures having higher breakdown voltage than the breakdown voltage of the active cell region. In one embodiment, the termination region includes superjunction structures having lower column charge as compared to the superjunction structures formed in the active cell region. In other embodiments, a superjunction power semiconductor device incorporating superjunction structures with slanted sidewalls where the grading of the superjunction columns in the termination region is reduced as compared to the column grading in the active cell region. The power semiconductor device is made more robust by ensuring any breakdown occurs in the core region as opposed to the termination region. Furthermore, the manufacturing process window for the power semiconductor device is enhanced to improve the manufacturing yield of the power semiconductor device.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan