Abstract: A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.

Abstract: A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.

Abstract: Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

Abstract: Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.

Abstract: Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

Abstract: A plurality of traffic profiles is determined for a plurality of traffic groups where each traffic profile includes a share of traffic and an address footprint size associated with a corresponding traffic group. A host write is received from a host and the traffic group that the host write belongs to is identified. Write data associated with the host write is stored in the solid state storage allocated to the traffic group that the host write is identified as belonging to where the amount of solid state storage allocated to each of the plurality of traffic groups is based at least in part on the traffic profile of a given traffic group.

Abstract: The present invention discloses a memory system and operating method thereof. The major features of the memory system and the method of operating thereof are identifying a stuck error pattern including failing constituent codes and decoding the stuck error pattern. The decoding the stuck error pattern is achieved by following steps: step 1 of using possible flipping patterns for decoding the failing constituent codes, and the number of the possible flipping patterns is 2 or more in accordance with at least the number of error bits, step 2 of obtaining a number of successfully decoded codewords after using the possible flipping patterns, and step 3 of selecting the most probable codeword from the number of successfully decoded codewords.

Abstract: Systems for performing turbo product code decoding includes an error intersection identifier determining a set of one or more error intersections using a set of error-containing codewords, and updating, based at least in part on Chase decoding performed on the set of error-containing codewords, the set of error intersections to obtain an updated set of one or more error intersections, a bit location selector suitable for selecting, from the set of error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords, and a Chase decoder performing Chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

Abstract: An apparatus for a turbo product codes includes a codeword generator and an interleaver. The codeword generator receives a data in a matrix, and generate a turbo product code (TPC) codeword including the data, row parities and column parities. The interleaver interleaves the TPC codeword by assigning at least one bit in at least one row-column intersection of the TPC codeword to at least one master code, and outputs the interleaved TPC codeword.

Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.

Abstract: A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value.

Abstract: Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

Abstract: An optimal read threshold estimation method includes determining a flip difference corresponding to an optimal step size ?opt, estimating a first slope m1 at a first read point and a second slope m2 at a second read point, and obtaining an optimal read threshold (XLPopt) as the intersection of a first line with the first slope m1 and a second line with the second slope m2.

Abstract: A soft output detector is programmed with a first set of parameters. Soft information is generated according to the first set of parameters, including likelihood information that spans a maximum likelihood range. Error correction decoding is performed on the soft information generated according to the first set of parameters. In the event decoding is unsuccessful, the soft output detector is programmed with a second set of parameters, soft information according is generated to the second set of parameters (including likelihood information that is scaled down from the maximum likelihood range), and error correction decoding is performed on the soft information generated according to the second set of parameters.

Abstract: A wear statistic associated with a wear metric distribution is determined, wherein the wear metric distribution is a distribution of a wear metric associated with a group of solid state storage cells. A wear-leveling period is determined, wherein the wear-leveling period is based at least in part on the wear statistic, wherein the wear-leveling period is a measure of time or operations between two wear-leveling operations performed on the group of solid state storage cells.

Abstract: A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET?1B+D)?1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.

Abstract: Decoding an LDPC encoded codeword is disclosed. Variable nodes corresponding to a parity check matrix of the LDPC encoded codeword have been divided into a plurality of groups. A selected group of variable nodes from the plurality of groups of variable nodes is updated. Check nodes are updated using a min-sum update. A selected input value provided from a variable node of the selected group of variable nodes and provided to a certain check node of the check nodes is discarded to be not available for use in a future min-sum update.

Abstract: Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.

Abstract: It is determined that a read count has reached one of a set of read count thresholds. An initial test page which corresponds to the read count threshold that has been reached is selected from a set of initial test pages. There is at least one page that is not in the set of initial test pages and is victimized by an offending page that also victimizes a page in the set of initial test pages. A test read is performed on the selected test page and the results of the test read of the selected test page are evaluated for read disturb noise.