Patents by Inventor Lingqi Zeng

Lingqi Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8943390
    Abstract: A codeword that is associated with one uncorrected codeword in a set of first codewords is selected from a set of third codewords. Error correction decoding is performed on the selected codeword using a third, systematic error correction code.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: January 27, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Yu Kou, Lingqi Zeng
  • Patent number: 8937838
    Abstract: An expected value associated with stored values in solid state storage, as well as a set of three or more points are obtained where the three or more points include a voltage and a value associated with stored values. Two points having ratios closest to the expected value are selected from the set. A voltage is determined based at least in part on the selected two points and the expected value.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 20, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Lingqi Zeng, Jason Bellorado, Frederick K. H. Lee, Arunkumar Subramanian
  • Publication number: 20150019926
    Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 15, 2015
    Inventors: Yu Kou, Lingqi Zeng
  • Publication number: 20150006981
    Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.
    Type: Application
    Filed: June 6, 2014
    Publication date: January 1, 2015
    Inventors: Yu Kou, Lingqi Zeng, Jason Bellorado, Marcus Marrow
  • Patent number: 8923062
    Abstract: A next read threshold is determined by determining a first number of solid state storage cells having a stored voltage which falls into a first voltage range and determining a second number of solid state storage cells having a stored voltage which falls into a second voltage range. A gradient is determine by taking a difference between the first number of solid state storage cells and the second number of solid state storage cells. The next read threshold is determined based at least in part on the gradient.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Arunkumar Subramanian, Lingqi Zeng, Xiangyu Tang, Ameen Aslam
  • Patent number: 8923066
    Abstract: A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Arunkumar Subramanian, Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Frederick K. H. Lee
  • Patent number: 8918696
    Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: December 23, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kin Man Ng, Kwok W. Yeung, Lingqi Zeng, Yu Kou, Aditi R. Ganesan
  • Patent number: 8914709
    Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: December 16, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng, Jason Bellorado, Marcus Marrow
  • Patent number: 8914705
    Abstract: A plurality of random bit sequences is generated. Each of the random bit sequences is different and is based at least in part on an input bit sequence. A plurality of metrics corresponding to the plurality of random bit sequences is generated. The plurality of metrics is associated with one or more transition run lengths. One of the random bit sequences is selected based at least in part on the metrics. An output bit sequence is generated that includes the selected random bit sequence and an index associated with demodulating the selected random bit sequence.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 16, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Lingqi Zeng, Yu Kou
  • Patent number: 8904263
    Abstract: A first set of one or more soft detector outputs is generated. It is determined if error correction decoding is successful using the first set of soft detector outputs. In the event it is determined error correction decoding is not successful, a second set of one or more soft detector outputs is generated where a largest likelihood associated with the first set is greater than a largest likelihood associated with the second set.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: December 2, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Naveen Kumar, Zheng Wu, Jason Bellorado, Lingqi Zeng, Marcus Marrow
  • Publication number: 20140325320
    Abstract: A set of one or more component syndromes associated with a turbo product code (TPC) codeword is obtained from a component syndrome buffer. Component decoding is performed on the set of one or more component syndromes.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 30, 2014
    Inventors: Arunkumar Subramanian, Naveen Kumar, Zheng Wu, Lingqi Zeng, Jason Bellorado
  • Publication number: 20140304480
    Abstract: An address is received. One or more neighbors associated with the received address is/are determined. One or more neighboring hot metrics is/are determined for the one or more neighbors associated with the received address. A hot metric for the received address is determined based at least in part on the neighboring hot metrics.
    Type: Application
    Filed: January 31, 2014
    Publication date: October 9, 2014
    Inventors: Xiangyu Tang, Frederick K.H. Lee, Jason Bellorado, Lingqi Zeng, Zheng Wu
  • Patent number: 8843812
    Abstract: A plurality of metrics associated with a plurality of partially decoded codewords is obtained. The plurality of partially decoded codewords has been processed at least once by a first soft output decoder and a second soft output decoder and the plurality of partially decoded codewords is stored in a memory. At least one of the plurality of partially decoded codewords is selected based at least in part on the plurality of metrics; the memory is instructed to vacate the at least one selected codeword.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: September 23, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Yu Kou, Lingqi Zeng
  • Patent number: 8819524
    Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: August 26, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Publication number: 20140233317
    Abstract: A victim group of one or more cells is read using a first read threshold to obtain a first raw read which includes one or more values. The victim group of cells is read using a second read threshold to obtain a second raw read which includes one or more values. A neighboring read, corresponding to a neighboring group of one or more cells associated with the victim group of cells, is obtained. A composite read is generated, including by selecting from at least the first raw read and the second raw read based at least in part on the neighboring read.
    Type: Application
    Filed: November 4, 2013
    Publication date: August 21, 2014
    Inventors: Jason Bellorado, Arunkumar Subramanian, Marcus Marrow, Zheng Wu, Lingqi Zeng
  • Publication number: 20140223264
    Abstract: A first message, associated with going from one of a plurality of variable nodes to one of a plurality of check nodes is computed, wherein: (1) one or more connections between the plurality of variable nodes and the plurality of check nodes are specified by an LDPC parity check matrix and (2) a scaling constant is used to compute the first message. A second message, associated with going from one of the plurality of check nodes to one of a plurality of variable nodes, is computed, wherein the scaling constant is not used to compute the second message.
    Type: Application
    Filed: November 18, 2013
    Publication date: August 7, 2014
    Inventors: Lingqi Zeng, Qiuju Diao, Jason Bellorado
  • Patent number: 8799752
    Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 5, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Publication number: 20140195877
    Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed on the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed on the data associated with the decoder.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 10, 2014
    Applicant: SK hynix memory solutions inc.
    Inventors: Lingqi Zeng, Yu Kou
  • Publication number: 20140143616
    Abstract: A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.
    Type: Application
    Filed: October 15, 2013
    Publication date: May 22, 2014
    Applicant: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Publication number: 20140140384
    Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 22, 2014
    Applicant: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng