Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract: The invention provides robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers are removed. An inside surface of the formed HSG polysilicon layer is nitridized to form a nitridation layer. A layer of cell nitride is deposited over the nitridation layer and the outside HSG polysilicon layer. A top electrode is formed over the deposited cell nitride layer.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion of the metal nitride further from the dielectric material is formed from a halogenated metal-containing precursor. The methodology of the present invention can be utilized for forming capacitor constructions, with the portion of the metal nitride formed from the halogenated metal-containing precursor being incorporated into a capacitor electrode.

Abstract: A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with hydrogen, oxygen and nitrous oxide gases to form an oxidation layer over the second layer. A third layer of a conductive material is formed over the second layer to thereby form the capacitor. While the capacitor exhibits an improved leakage current reduction, overall capacitance is substantially unaffected, as compared to a similar capacitor having an oxidation layer built from a combination of oxygen and hydrogen gases only.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50?.

Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection.

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection.

Abstract: Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with hydrogen, oxygen and nitrous oxide gases to form an oxidation layer over the second layer. A third layer of a conductive material is formed over the second layer to thereby form the capacitor. While the capacitor exhibits an improved leakage current reduction, overall capacitance is substantially unaffected, as compared to a similar capacitor having an oxidation layer built from a combination of oxygen and hydrogen gases only.

Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.

Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.

Abstract: The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.

Abstract: The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: The invention provides robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers are removed. An inside surface of the formed HSG polysilicon layer is nitridized to form a nitridation layer. A layer of cell nitride is deposited over the nitridation layer and the outside HSG polysilicon layer. A top electrode is formed over the deposited cell nitride layer.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.