Abstract: Semiconductor devices are provided with double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, container capacitors for a semiconductor device have a cup-shaped bottom electrode with an interior surface including HSG polysilicon and an exterior surface including smooth polysilicon. A barrier layer may be formed within the container that defines the container capacitor.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A memory cell container of a DRAM semiconductor memory device and method for manufacturing the cell container are provided. The cell includes a container formed in a structural layer such as borophosphosilicate glass. The container is then lined with a polysilicon such as hemispherical grained polysilicon. A dielectric layer is deposited over the polysilicon layer. A barrier layer is deposited over the dielectric layer such that the opening of the container is covered but not the sidewalls or the bottom of the container. The cell is then oxidized and the barrier layer provides protection as an oxygen barrier during the oxidation or any following reoxidation process.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: The invention provides robust and cost effective techniques to fabricate double-sided HSG electrodes for container capacitors. In one embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. A barrier layer is then formed over the formed HSG polysilicon layer. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers is then removed. A portion of outside surfaces of the formed HSG polysilicon is then exposed by removing the substrate, while the barrier layer is still on the interior surface of the container to prevent formation of sink holes and to prevent stringer problems during removal of the substrate. The barrier layer is then removed to expose the interior surfaces of the HSG polysilicon to form the double-sided HSG electrode.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: A memory cell container of a DRAM semiconductor memory device and method for manufacturing the cell container are disclosed. The cell includes a container formed in a structural layer such as borophosphosilicate glass. The container is then lined with a polysilicon such as hemispherical grained polysilicon. A dielectric layer is deposited over the polysilicon layer. A barrier layer is deposited over the dielectric layer such that the opening of the container is covered but not the sidewalls or the bottom of the container. The cell is then oxidized and the barrier layer provides protection as an oxygen barrier during the oxidation or any following re-oxidation process.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-containing substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-containing gas to desposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen-containing gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-containing substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with hydrogen, oxygen and nitrous oxide gases to form an oxidation layer over the second layer. A third layer of a conductive material is formed over the second layer to thereby form the capacitor. While the capacitor exhibits an improved leakage current reduction, overall capacitance is substantially unaffected, as compared to a similar capacitor having an oxidation layer built from a combination of oxygen and hydrogen gases only.

Abstract: The invention provides robust and cost effective techniques to fabricate double-sided HSG electrodes for container capacitors. In one embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. A barrier layer is then formed over the formed HSG polysilicon layer. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers is then removed. A portion of outside surfaces of the formed HSG polysilicon is then exposed by removing the substrate, while the barrier layer is still on the interior surface of the container to prevent formation of sink holes and to prevent stringer problems during removal of the substrate. The barrier layer is then removed to expose the interior surfaces of the HSG polysilicon to form the double-sided HSG electrode.

Abstract: A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing the insulative layer to expose the polysilicon layer outside the container; nitridizing the exposed polysilicon layer at a low temperature, preferably by remote plasma nitridation; removing the barrier layer to expose the inner surface of the polysilicon layer within the container; and forming HSG polysilicon over the inner surface of the polysilicon layer. The capacitor can be completed by forming a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer. The cup-shaped bottom electrode formed within the container defines an interior surface comprising HSG polysilicon, and an exterior surface comprising smooth polysilicon.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.