Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: Certain aspects of a method and system for receiving audio, video and data services with advanced television systems committee (ATSC) enabled television sets may be provided. Aspects of the method may include conversion of a plurality of received quadrature amplitude modulated (QAM) signals into a plurality of vestigial side band (VSB) signals within a set-top box. The set top box may tune to each of the plurality of received QAM signals and demodulate each of the plurality of received QAM signals into a plurality of bitstreams and demultiplex the plurality of bitstreams. The demultiplexed plurality of bitstreams may be modulated into a plurality of VSB signals. The plurality of VSB signals may be modulated into a plurality of RF signals. One or more of the plurality of RF signals may be communicated to at least one of a plurality of VSB enabled television sets.

Abstract: A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A resampling application specific integrated circuit (RSA) supports image interpolation or decimation by any arbitrary factor in order to provide flexibility, and utilizes a neighborhood of up to 9.times.9 pixels to produce image data of high quality. The RSA contains a separate vertical and horizontal filter units for vertical resizing and horizontal resizing operations, vertical and horizontal position accumulator units, a configuration register unit for loading the vertical and horizontal position accumulator units, and a memory management unit to interface the RSA to external memory banks. The vertical and horizontal filter units contain nine multipliers and nine corresponding coefficient memories, with each memory preferably containing storage space for thirty-two coefficients. The coefficients are addressed on a pixel by pixel basis in response to the outputs of the vertical and horizontal position accumulator units.

Abstract: A system architecture is provided that includes an image sensor unit operable in a single channel mode and a dual channel mode. The image sensor unit includes an electronic image sensor comprising a row and column array of pixel elements, wherein the rows of the array having a line length of N pixels. First and second digital signal processing units for processing image data generated by the image sensor unit into color component image data are provided, wherein each of said first and second digital signal processing units has a line length processing capacity less than N pixels.

Abstract: A color filter array for use with an electronic image sensor is disclosed, wherein the red and blue filter elements of the color filter array are arranged to correspond with an interleaved chrominance channel pattern. Thus, actual red and blue values are utilized to generate interleaved chrominance channel information instead of interpolated values as required by conventional CFA patterns.

Abstract: A single integrated circuit device is disclosed that is capable of selectively functioning in real time as either a sequential matrix multiplier, a parallel matrix multiplier, a convolver or a finite input response FIR filter in order to process image data. A core group of multipliers is used to provide the basic multiplication operation that is common to each of the desired image processing functions. Input data router unit, coefficient router units and an output data router unit are responsive to mode selection control signals, supplied to a mode selection port, to route the appropriate input data and coefficients to the core group of multipliers and to route the output of the adders to the correct output port(s) for each of the desired processing functions.

Abstract: An integrated circuit that uses the same coefficient registers, multipliers and adders to perform both matrix multiplication and convolution operations. The multipliers are arranged in columns and rows with the matrix multiplication adders located in the corresponding columns and with the adder for producing the convolution output located in one of the columns. A mode selection switch causes the multiplexers to change input data routing based on the mode selected. The circuit allows loading of all the coefficients or selection of hardwired coefficients. By rerouting the inputs of the multipliers using the multiplexers, the circuit can be easily configured for either mode of operation. The outputs corresponding to the columns are either output directly during matrix multiplication or provided to the convolution adder.

Abstract: A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line and write enable line, and a pointer unit for addressing the read enable lines and the write enable lines to permit data to be written into the word storage locations in a first sequence in a first operating mode and to be retrieved from the word storage locations in a second sequence that is transposed from the first sequence in a second operating mode; and a clock generator coupled to the pointer unit which controls the operation of the pointer unit.

Abstract: A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit is employed to sequentially address a plurality of word storage locations provided in a storage unit. The pointer unit includes a number of shift-registers that sqeuentially shift a logic "1" along the length of the pointer unit to accomplish the addressing.

Abstract: A signal processing circuit operates upon digitized signals from a plurality of linear color sensors that are spatially separated in the page scanning direction by a predetermined number of lines. The digitized signals are realigned in a line rephasing circuit, which provides sets of rephased color values for each scanned element of the original. A matrix multiplication is performed in a row sequential process upon the rephased signals by a group of multipliers, one multiplier for each row coefficient of the matrix. Each multiplier receives a rephased signal and a series of coefficients multiplexed into the circuit from a group of row coefficient registers. By clocking the rephased signals at a submultiple of the coefficient rate, a row-sequential matrix operation is serially performed in a pipelined manner.

Abstract: A correction circuit processes digitized signals from an image sensor and generates gain correction values to compensate for variations in the output of the sensor. While imaging a gain calibration object, the sensor is operated in a calibration mode in which a plurality of calibration values are generated that pertain to each photosite. The digitized calibration values are transformed into log space for processing by a gain level averaging circuit. The log calibration signals are first subtracted from a reference corresponding to a maximum expected signal value. The difference signals are serially accumulated by means of pair of registers and an adder, and the sum is stored in a gain memory. In a subsequent normal operating mode, the summed signals for each photosite are retrieved from the gain memory and bit-shifted to form an average correction value for each photosite.

Abstract: A digital correlated double sampling circuit employs three registers and a single clock signal to sample the output of a charge transfer device. The first register samples the reset reference value on the falling edge of the master clock cycle while the remaining two registers sample on the rising edge. The second register samples the image level and the third register samples the output of the first register, thus effecting a delay of the reset reference level. The outputs of the second and third registers, that is, the image level and the reset reference level, are differenced to provide a noise-free image signal.

Abstract: A digital processing architecture for a high resolution image sensor uses a plurality of like digital processors for time-divided processing of the output of the sensor. Each processor is operational according to start and stop signals from a programmable sequencer. In a preferred embodiment, two sets of processors handle a line resolution of 1024 pixels, one set doing the first half of each line and the other set doing the second half. This is of particular utility where vertical processing is required, and the full line delays needed are divided into partial resettable delays resident in each of the processors.

Abstract: A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit is employed to sequentially address a plurality of word storage locations provided in a storage unit. The pointer unit includes a number of shift-registers that sequentially shift a logic "1" along the length of the pointer unit to accomplish the addressing.

Abstract: A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line and write enable line, and a pointer unit for addressing the read enable lines and the write enable lines to permit data to be written into the word storage locations in a first sequence in a first operating mode and to be retrieved from the word storage locations in a second sequence that is transposed from the first sequence in a second operating mode; and a clock generator coupled to the pointer unit which controls the operation of the pointer unit.

Abstract: A clock generator for producing a pulse that can be adjusted in width and position. The positive edge of an incoming clock signal is slowed by an adjustable rise time inverter with a selected bias voltage until a selected threshold voltage level is met by a Schmitt trigger. The output from the Schmitt trigger is directed through a similar delay circuit to establish the pulse width of the pulse.

Abstract: A digital processing system is described for processing luminance and chrominance signals from a single, multi-color image sensor. By concentrating signal improvements and corrections into an application-dependent post-processing phase, the pre-processing functions are isolated in a signle, generic pre-processor integrated circuit that provides fully interpolated color signals in a real-time system by utilizing a fully pipelined architecture. The pre-processor circuit separates luminance and chrominance interpolation so as to operate partly in quantized linear space and partly in quantized logarithmic space. The image signals are processed in a black reference clamp, a defect concealment circuit and a color separation and luminance interpolation circuit in linear space, using right shifts and additions to approximate predetermined multiplications. The signals are then transformed into hue signals and processed in log space for white balance and chroma (hue) interpolation.