Abstract: The circuit includes a cascaded array of digital circuit blocks that together implement a matrix multiplication in each channel of a color video signal processing system. Each circuit block includes two registers for multiplying or dividing two input digital signals by respective powers of two according to programmable bit shifts. The resultant signals are arithmetically combined according to a programmable arithmetic function to provide an output signal. By mask programming the arithmetic function and the bit lenghts of the shifts for each block and by cascading the programmed blocks, the multipler coefficients of the matrix are established and the output signal represents a specified color matrix operation.

Abstract: In a signal processing network including a color correction matrix and gamma compensation, detail processing is disclosed that includes a detail extraction circuit for generating a detail signal from an un-matrixed green signal and a detail enhancement circuit for adding the detail signal to the matrixed, gamma-corrected red, green and blue signals. The un-matrixed green signal is converted to a gamma-corrected green signal and separately input to vertical and horizontal high pass filters, which separate detail components representative of vertical and horizontal detail, respectively. The vertical detail is additionally input to a horizontal low pass filter to eliminate excessive enhancement of diagonal image components. The detail components are cored and input to the detail enhancement circuit.