Patents by Inventor Lionel S. White, Jr.

Lionel S. White, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5251168
    Abstract: By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: October 5, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Gishi Chung, William R. McKee, William F. Richardson, Lionel S. White, Jr.
  • Patent number: 4868823
    Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.
    Type: Grant
    Filed: January 15, 1988
    Date of Patent: September 19, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., Joseph H. Neal, Bao G. Tran
  • Patent number: 4748349
    Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
    Type: Grant
    Filed: October 27, 1987
    Date of Patent: May 31, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4654849
    Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: March 31, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., Joseph H. Neal, Bao G. Tran
  • Patent number: 4642784
    Abstract: Proven data base is generated for electrical test responses of sporadic defects in integrated circuits as manufactured. Manufactured circuits are subjected to that electrical testing and resulting responses used to identify defect and check the manufacture to avoid its repetition.
    Type: Grant
    Filed: April 26, 1984
    Date of Patent: February 10, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., Maury Zivitz
  • Patent number: 4543500
    Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled drive transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
    Type: Grant
    Filed: October 22, 1980
    Date of Patent: September 24, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4543501
    Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: September 24, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4533843
    Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: August 6, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4418293
    Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
    Type: Grant
    Filed: October 22, 1980
    Date of Patent: November 29, 1983
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4401904
    Abstract: A random access read/write MOS memory device or the like employs a delay circuit in clock generators to produce small increments of delay. The delay circuit consists of a field effect transistor connected as a transfer device with its gate precharged and the gate-to-source capacitance much larger than the parasitics of the gate node. A larger transistor may be connected to the output node to improve the output waveform by holding down the output voltage at the beginning of a cycle.
    Type: Grant
    Filed: March 24, 1980
    Date of Patent: August 30, 1983
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., Ngai H. Hong
  • Patent number: 4370575
    Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
    Type: Grant
    Filed: October 14, 1980
    Date of Patent: January 25, 1983
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4352996
    Abstract: A random access read/write MOS memory device or the like employs a clock driver circuit which includes a push-pull type output stage with two transistors having a clock .PHI. and its complement .PHI. as gate inputs. An output node is pulled to a full supply voltage level by a pump transistor connecting the output node to the supply and having a delayed clock coupled to its gate. Another transistor with the supply voltage on its gate connects the output node to the gate of the pump transistor.
    Type: Grant
    Filed: March 21, 1980
    Date of Patent: October 5, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Lionel S. White, Jr.
  • Patent number: 4344157
    Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh address generator circuitry including an address counter or commutator and a multiplexer to insert the refresh address when a command is received or internally generated indicating a refresh cycle. If a refresh command is not being executed, the device is accessed in the usual manner if a memory address is received.
    Type: Grant
    Filed: March 28, 1980
    Date of Patent: August 10, 1982
    Assignee: Texas Instruments Incorporated
    Inventors: Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4330851
    Abstract: A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.
    Type: Grant
    Filed: March 21, 1980
    Date of Patent: May 18, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Lionel S. White, Jr.
  • Patent number: 4330852
    Abstract: A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.
    Type: Grant
    Filed: November 23, 1979
    Date of Patent: May 18, 1982
    Assignee: Texas Instruments Incorporated
    Inventors: Donald J. Redwine, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4321695
    Abstract: A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.
    Type: Grant
    Filed: November 23, 1979
    Date of Patent: March 23, 1982
    Assignee: Texas Instruments Incorporated
    Inventors: Donald J. Redwine, Lionel S. White, Jr.
  • Patent number: 4288706
    Abstract: A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.
    Type: Grant
    Filed: October 20, 1978
    Date of Patent: September 8, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund A. Reese, Lionel S. White, Jr., Joseph C. McAlexander, III
  • Patent number: 4286178
    Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit at the center of each column. Instead of a single pair of cross-coupled driver transistors forming the bistable circuit, dual parallel pairs are used. One pair used in the initial sensing has a long channel length so that the pair may be more readily matched, while the other pair used later in the cycle for driving the zero-going side of the column line to ground has a shorter channel to enhance speed.
    Type: Grant
    Filed: June 12, 1978
    Date of Patent: August 25, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: G. R. Mohan Rao, Lionel S. White, Jr.
  • Patent number: 4281401
    Abstract: A semiconductor memory device of the MOS/LSI type using an array of dynamic one-transistor cells has a high speed serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.
    Type: Grant
    Filed: November 23, 1979
    Date of Patent: July 28, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: Donald J. Redwine, Lionel S. White, Jr., G. R. Mohan Rao
  • Patent number: 4280070
    Abstract: A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.
    Type: Grant
    Filed: October 20, 1978
    Date of Patent: July 21, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund A. Reese, Lionel S. White, Jr., Joseph C. McAlexander, III