Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit of the dynamic type at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. A coupling transistor connects each column line half to one of the cross-coupled driver transistors of the bistable circuit. The coupling transistors are of the depletion mode type and each has its gate connected to the sense node on the opposite side between the other coupling transistor and driver transistor.

Abstract: A semiconductor memory device forming a static type memory cell uses three field effect transistors. One is connected between a storage node and a bit line so it functions as an access transistor. The storage node is connected to a refresh node through a second transistor having its gate shorted to drain, and the third transistor connects the refresh node to a supply voltage. A voltage dependent capacitor connects the refresh node to a refresh clock. A logic 1 on the storage node turns on the third transistor and charges the refresh node, which turns on the capacitor so the refresh clock is coupled through to turn on the second transistor and refresh the storage node. When a logic 0 is stored, this will not happen.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry including an address counter and a multiplexer to insert the refresh address when a system command is received indicating a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is not present, the device is accessed in the usual manner.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with sense amplifier circuits at the center of each column and an intermediate output buffer having inputs connected to both sides of the column lines. The intermediate output buffer is a bistable circuit wherein the load transistors have clock voltages applied to their gates after an initial sensing period, so the initial sensing of data on the column lines is done without loads. After this initial period, the load transistors are turned on by booting capacitors. Then, transistors shunting the gates of the load devices to the sense nodes function to turn off the load device on the zero logic level side. The gates of these shunting transistors are each controlled by the voltages on the sense node on the opposite side of the bistable circuit.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have clock voltages applied to their gates after an initial sensing period, so the initial sensing is done without loads for the bistable circuit. After this initial period, the load transistors are turned on by boosting capacitors. Then, fixed biased transistors shunting the gates of the load device to the digit lines function to turn off the load device on the zero logic level side.

Abstract: Disclosed is a read clock generator for use in a semiconductor memory. The read clock generator is comprised of a bistable amplifier and a differential voltage sensor. The bistable amplifier is activated during a read cycle; and it simulates the transient operation of a plurality of sense amplifiers which sense binary information stored within the memory. The differential voltage sensor couples to the bistable amplifier, and produces an output signal when the bistable amplifier stabilizes.