Abstract: A semiconductor structure is provided that includes a pFET located in a pFET device region, the pFET includes a first functional gate structure and a plurality of pFET semiconductor channel material nanosheets, and an nFET located in the nFET device region, the nFET includes a second functional gate structure and a plurality of pFET semiconductor channel material nanosheets. The pFET semiconductor channel material nanosheets can be staggered relative to, or vertically aligned in a horizontal direction with, the nFET semiconductor channel material nanosheets. When staggered, a bottom dielectric isolation structure can be located in both the device regions, and the second functional gate structures has a bottommost surface that extends beneath a topmost surface of the bottom dielectric isolation structure. When horizontally aligned, a vertical dielectric pillar is located between the two device regions.

Abstract: A semiconductor device includes power rails formed in a backside of a wafer. A gate of a first transistor on the wafer is connected to a power rail through a via-to-backside power rail (VBPR) gate contact. A source/drain (S/D) region of a second transistor on the wafer is connected to a power rail through a VBPR S/D contact. The VBPR gate contact partially vertically overlaps a gate cut region between the first transistor and the second transistor.

Abstract: A semiconductor structure includes a source/drain region; a frontside source/drain contact disposed on the source/drain region, a via-to-backside power rail disposed on the frontside source/drain contact and on a portion of the source/drain region, and a backside power rail connected to the via-to-backside power rail.

Abstract: A semiconductor device includes a backside power rail; a transistor source/drain structure that has a backside facing the backside power rail and has a frontside facing away from the backside power rail; and a via disposed between and electrically connecting the backside power rail and the source/drain structure. The via includes a buried portion that is disposed between the backside power rail and the backside of the transistor source/drain structure. A part of the buried portion overlaps and contacts at least a part of the backside of the source/drain structure. The via also includes a side portion that is electrically connected with the buried portion and extends along a vertical side of the source/drain structure between the frontside and the backside; and a top portion that is electrically connected with the side portion and covers at least a part of the frontside of the source/drain structure.

Abstract: A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.

Abstract: A semiconductor device, such as an integrated circuit, microprocessor, wafer, or the like, includes a first gate all around field effect transistor (GAA FET) and second GAA FET within the same region type (e.g., p-type region or n-type region, etc.) with relatively heterogenous channels within the same region. The first GAA FET includes a plurality of first channels of a first channel material (e.g., SiGex cladded channels). A second GAA FET includes a plurality of second channels of a second channel material (e.g., SiGey cladded channels, Si channels, or the like). The GAA FETs may have different channel structures, such as relatively different channel lengths. The heterogenous channels may provide improved GAA FET device performance by allowing an ability to tune or adjust channel mobility of GAA FETs in similar region types in different locations or when utilized in different applications.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.

Abstract: Semiconductor devices and methods of forming the same include a semiconductor base having a first width. A semiconductor device over the semiconductor base has a second width that is greater than the first width. A power rail is beneath the semiconductor base. A conductive contact extends from a top of the semiconductor device to the power rail.

Abstract: A semiconductor device includes a first transistor including a first source/drain region, and a second transistor stacked on the first transistor. The second transistor includes a second source/drain region. The semiconductor device further includes a via structure disposed between a power element and the second source/drain region. The via structure includes a first via disposed on the power element, and a second via disposed on the first via, wherein the second via is angled with respect to the first via.

Abstract: Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first transistor device on a substrate, a second transistor device on the substrate, and a power rail between the first transistor device and the second transistor device. The power rail may include a first section with a first critical dimension (CD), a second section with a second CD, and a third section with a third CD.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first top transistor comprising a first source/drain (S/D) region and a first bottom transistor with a second S/D region. The first bottom transistor may be stacked directly below the first transistor. The semiconductor structure may also include a backside power delivery network (BSPDN) below the bottom transistor, a back-end-of-line (BEOL) metal level above the top transistor, and a first interlevel via electrically connecting a top of the first S/D region to the BSPDN.

Abstract: An approach forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first wiring interconnect structure, and a third wiring interconnect structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.

Abstract: A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

Abstract: A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.

Abstract: One illustrative IC product disclosed herein includes a semiconductor substrate and a first transistor device formed on the semiconductor substrate. The first transistor device comprises a first gate structure. The first gate structure comprises a gate insulation layer, a first layer of titanium nitride (TiN) positioned above the gate insulation layer, a layer of titanium silicon nitride (TiSiN) positioned above the first layer of TiN and a second layer of titanium nitride (TiN) positioned above the layer of TiSiN.

Abstract: One illustrative IC product disclosed herein includes a semiconductor substrate and a first transistor device formed on the semiconductor substrate. The first transistor device comprises a first gate structure. The first gate structure comprises a gate insulation layer, a first layer of titanium nitride (TiN) positioned above the gate insulation layer, a layer of titanium silicon nitride (TiSiN) positioned above the first layer of TiN and a second layer of titanium nitride (TiN) positioned above the layer of TiSiN.

Abstract: A method and apparatus are provided for automatically controlling the position of the spray bars and nozzles and the spray flow of a CMP in-situ cleaning module. Embodiments include fixing a wafer to a CMP cleaning module, the cleaning module having a first and a second group of spray bars and nozzles, the first and second groups of spray bars and nozzles being located proximate to opposite surfaces of the wafer; cleaning one or more of the surfaces of the wafer with a chemical spray forced through at least one of the groups of spray bars and nozzles; determining a measured profile of the one or more surfaces of the wafer; comparing the measured profile against a target profile; and adjusting automatically at least one of the first and second groups of spray bars and nozzles relative to the one or more surfaces of the wafer based on the comparison.