Abstract: A system for efficiently interconnecting computing nodes can include a plurality of computing nodes and a plurality of network switches coupled in parallel to the plurality of computing nodes. The system can also include a plurality of node interfaces. Each computing node among the plurality of computing nodes can include at least one node interface for each network switch among the plurality of network switches. The plurality of node interfaces corresponding to a computing node can be configured to send data to another computing node via the plurality of network switches. The system can also include a plurality of switch interfaces. Each network switch among the plurality of network switches can include at least one switch interface for each computing node among the plurality of computing nodes. A switch interface corresponding to the computing node can be coupled to a node interface corresponding to the computing node.

Abstract: Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.

Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of optical transceivers that facilitate free-space optical communications among the plurality of computing nodes. The system may ensure a line of sight between the plurality of computing nodes and the optical transceivers to facilitate the free-space optical communications. The line of sight may be preserved by the position or placement of the computing nodes in the system. The position or placement of the computing nodes may be achieved by using different shaped enclosures for holding the computing nodes.

Abstract: A system for efficiently interconnecting computing nodes can include a plurality of computing nodes and a plurality of network switches coupled in parallel to the plurality of computing nodes. The system can also include a plurality of node interfaces. Each computing node among the plurality of computing nodes can include at least one node interface for each network switch among the plurality of network switches. The plurality of node interfaces corresponding to a computing node can be configured to send data to another computing node via the plurality of network switches. The system can also include a plurality of switch interfaces. Each network switch among the plurality of network switches can include at least one switch interface for each computing node among the plurality of computing nodes. A switch interface corresponding to the computing node can be coupled to a node interface corresponding to the computing node.

Abstract: A system for interconnecting a plurality of computing nodes includes a plurality of optical circuit switches and a plurality of electrical circuit switches. A first network stage comprises a first plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each computing node among the plurality of computing nodes is optically coupled to at least one of the first plurality of circuit switches. A second network stage comprises a second plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each circuit switch among the first plurality of circuit switches is optically coupled to each circuit switch among the second plurality of optical circuit switches.

Abstract: Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.

Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of node optical transceivers that are electrically coupled to at least some of the plurality of computing nodes. The system can also include a plurality of router optical transceivers that facilitate free-space optical communications with the plurality of node optical transceivers. Each node optical transceiver among the plurality of node optical transceivers can have a corresponding router optical transceiver that is optically coupled to the node optical transceiver. The system can also include a router that is coupled to the plurality of router optical transceivers. The router can be configured to route the free-space optical communications among the plurality of computing nodes.

Abstract: Methods and systems related to memory reduction in a system by oversubscribing physical memory shared among compute entities are provided. A portion of the memory includes a combination of a portion of a first physical memory of a first type and a logical pooled memory associated with the system. A logical pooled memory controller is configured to: (1) track both a status of whether a page of the logical pooled memory allocated to any of the plurality of compute entities is a known-pattern page and a relationship between logical memory addresses and physical memory addresses associated with any allocated logical pooled memory, and (2) allow the write operation to write data to any available space in the second physical memory of the first type only up to an extent of physical memory that corresponds to the portion of the logical pooled memory previously allocated to the compute entity.

Abstract: A system for interconnecting a plurality of computing nodes includes a plurality of optical circuit switches and a plurality of electrical circuit switches. A first network stage comprises a first plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each computing node among the plurality of computing nodes is optically coupled to at least one of the first plurality of circuit switches. A second network stage comprises a second plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each circuit switch among the first plurality of circuit switches is optically coupled to each circuit switch among the second plurality of optical circuit switches.

Abstract: Methods and systems related to memory reduction in a system by oversubscribing physical memory shared among compute entities are provided. A portion of the memory includes a combination of a portion of a first physical memory of a first type and a logical pooled memory associated with the system. A logical pooled memory controller is configured to: (1) track both a status of whether a page of the logical pooled memory allocated to any of the plurality of compute entities is a known-pattern page and a relationship between logical memory addresses and physical memory addresses associated with any allocated logical pooled memory, and (2) allow the write operation to write data to any available space in the second physical memory of the first type only up to an extent of physical memory that corresponds to the portion of the logical pooled memory previously allocated to the compute entity.

Abstract: A system for interconnecting a plurality of computing nodes includes a plurality of optical circuit switches and a plurality of electrical circuit switches. A first network stage comprises a first plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each computing node among the plurality of computing nodes is optically coupled to at least one of the first plurality of circuit switches. A second network stage comprises a second plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each circuit switch among the first plurality of circuit switches is optically coupled to each circuit switch among the second plurality of optical circuit switches.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.

Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of optical transceivers that facilitate free-space optical communications among the plurality of computing nodes. The system may ensure a line of sight between the plurality of computing nodes and the optical transceivers to facilitate the free-space optical communications. The line of sight may be preserved by the position or placement of the computing nodes in the system. The position or placement of the computing nodes may be achieved by using different shaped enclosures for holding the computing nodes.

Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of optical transceivers that facilitate free-space optical communications among the plurality of computing nodes. The system may ensure a line of sight between the plurality of computing nodes and the optical transceivers to facilitate the free-space optical communications. The line of sight may be preserved by the position or placement of the computing nodes in the system. The position or placement of the computing nodes may be achieved by using different shaped enclosures for holding the computing nodes.

Abstract: Methods and systems related to memory reduction in a system by oversubscribing physical memory shared among compute entities are provided. A portion of the memory includes a combination of a portion of a first physical memory of a first type and a logical pooled memory associated with the system. A logical pooled memory controller is configured to: (1) track both a status of whether a page of the logical pooled memory allocated to any of the plurality of compute entities is a known-pattern page and a relationship between logical memory addresses and physical memory addresses associated with any allocated logical pooled memory, and (2) allow the write operation to write data to any available space in the second physical memory of the first type only up to an extent of physical memory that corresponds to the portion of the logical pooled memory previously allocated to the compute entity.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for managing tracked memory usage data and performing various actions based on memory usage data tracked by a memory controller on a memory device. For example, systems described herein involve collecting and compiling data across one or more memory controllers to evaluate characteristics of the memory usage data to determine hotness metric(s) for segments of a memory resource. The systems described herein may perform a variety of segment actions based on the hotness metric(s). In addition, the systems described herein can compile the memory usage data according to one or more access granularities. This compiled data may further be shared with multiple accessing agents in accordance with access resolutions of the respective accessing agents.

Abstract: A system for interconnecting a plurality of computing nodes includes a plurality of optical circuit switches and a plurality of electrical circuit switches. A first network stage comprises a first plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each computing node among the plurality of computing nodes is optically coupled to at least one of the first plurality of circuit switches. A second network stage comprises a second plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each circuit switch among the first plurality of circuit switches is optically coupled to each circuit switch among the second plurality of optical circuit switches.

Abstract: A system for efficiently interconnecting computing nodes can include a plurality of computing nodes and a plurality of network switches coupled in parallel to the plurality of computing nodes. The system can also include a plurality of node interfaces. Each computing node among the plurality of computing nodes can include at least one node interface for each network switch among the plurality of network switches. The plurality of node interfaces corresponding to a computing node can be configured to send data to another computing node via the plurality of network switches. The system can also include a plurality of switch interfaces. Each network switch among the plurality of network switches can include at least one switch interface for each computing node among the plurality of computing nodes. A switch interface corresponding to the computing node can be coupled to a node interface corresponding to the computing node.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.