Patents by Inventor Li-Ting Wang
Li-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12628401Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.Type: GrantFiled: May 25, 2022Date of Patent: May 12, 2026Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Shun Chang, Kuo-Ju Chen, Sih-Jie Liu, Wei-Fu Wang, Yi-Chao Wang, Li-Ting Wang, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12628606Abstract: An intensity of a power laser beam applied to a semiconductor device is adjusted. An applied intensity of the power laser beam is indicative of a magnitude at which the power laser beam is emitted toward the semiconductor device and a reflection intensity of a probing laser beam applied to the semiconductor device is indicative of an emissivity of the semiconductor device. The reflection intensity of the probing laser beam is measured to determine the emissivity of the semiconductor device and the applied intensity of the power laser beam is adjusted as a function of the emissivity.Type: GrantFiled: May 17, 2022Date of Patent: May 12, 2026Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-Fu Wang, Yi-Chao Wang, Li-Ting Wang, Yee-Chia Yeo
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Publication number: 20260062836Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: ApplicationFiled: November 4, 2025Publication date: March 5, 2026Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20250368809Abstract: A resin composition is provided. The resin composition includes a resin mixture (A), a liquid rubber resin (B), an organic filler (C), a catalyst (D) and a siloxane coupling agent (E). The resin mixture (A) includes a bismaleimide resin.Type: ApplicationFiled: July 17, 2024Publication date: December 4, 2025Applicant: NAN YA PLASTICS CORPORATIONInventors: Ching-Yao Yuan, Hung-Yi Chang, Li-Ting Wang, Wei-Ru Huang
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Patent number: 12486597Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: GrantFiled: August 10, 2023Date of Patent: December 2, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20250364270Abstract: Provided is a device including a fin structure and methods for forming such a device. A method includes forming a layer of semiconductor material over a surface, wherein the layer of semiconductor material has a thickness; forming a layer of insulating material over the layer of semiconductor material, wherein the layer of insulating material comprises a first region with a thinner thickness and a second region with a thicker thickness greater than the thinner thickness; and performing a thermal anneal process to reduce the thickness of the layer of semiconductor material and to reduce a difference between the thinner thickness and the thicker thickness of the layer of insulating material.Type: ApplicationFiled: August 4, 2025Publication date: November 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yang Lu, Tz-Shian Chen, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12480223Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: GrantFiled: July 16, 2021Date of Patent: November 25, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20250357142Abstract: A manufacturing tool includes a probe laser and a pyrometer under control of a controller. The manufacturing tool may be configured to impinge radiation from the laser upon a wafer and to detected reflected light from the wafer by the pyrometer to determine a first reflectivity of a first anneal region on the wafer, and to determine a second reflectivity of a second anneal region on the wafer. The tool may be further configured to perform a first laser shot on the first anneal region, measure a first temperature of the first anneal region, and perform a second laser shot on a second anneal region. A power of the first laser shot is set in accordance with the first reflectivity. A power of the second laser shot is set in accordance with the second reflectivity.Type: ApplicationFiled: August 6, 2025Publication date: November 20, 2025Inventors: Tz-Shian Chen, Li-Ting Wang, Yee-Chia Yeo
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Publication number: 20250351510Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.Type: ApplicationFiled: July 20, 2025Publication date: November 13, 2025Inventors: Po-Kang Ho, Kuo-Ju Chen, Wei-Ting Chang, Wei-Fu Wang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo, Yi-Chao Wang, Tsai-Yu Huang
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Patent number: 12469717Abstract: A method of manufacturing a semiconductor device includes: determining a first reflectivity of a first anneal region on a wafer; determining a second reflectivity of a second anneal region on the wafer, performing a first laser shot on the first anneal region, measuring a first temperature of the first anneal region, and performing a second laser shot on a second anneal region. A power of the first laser shot is set in accordance with the first reflectivity. A power of the second laser shot is set in accordance with the second reflectivity.Type: GrantFiled: August 27, 2021Date of Patent: November 11, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Shian Chen, Li-Ting Wang, Yee-Chia Yeo
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Publication number: 20250343069Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.Type: ApplicationFiled: July 17, 2025Publication date: November 6, 2025Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12451390Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.Type: GrantFiled: March 13, 2023Date of Patent: October 21, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250318207Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.Type: ApplicationFiled: June 19, 2025Publication date: October 9, 2025Inventors: Yi-Yun Li, Tsai-Yu Huang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250318262Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.Type: ApplicationFiled: June 18, 2025Publication date: October 9, 2025Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250311351Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: ApplicationFiled: June 12, 2025Publication date: October 2, 2025Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Patent number: 12414338Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.Type: GrantFiled: May 13, 2022Date of Patent: September 9, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Yun Li, Tsai-Yu Huang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12399067Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.Type: GrantFiled: August 30, 2021Date of Patent: August 26, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tz-Shian Chen, Yi-Chao Wang, Wen-Yen Chen, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250254906Abstract: A method includes a number of operations. A semiconductor fin is formed and extends from a substrate. A dummy gate structure is formed across the semiconductor fin. An exposed surface of the gate layer is converted into a surface modification layer over the gate layer. Source/drain regions are formed on the semiconductor fin. The dummy gate structure is removed. A gate structure is formed over the semiconductor fin and extends between the source/drain regions and in the surface modification layer.Type: ApplicationFiled: February 6, 2024Publication date: August 7, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Kang HO, Tsai-Yu Huang, Li-Ting Wang, Chi On CHUI
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Patent number: 12369394Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.Type: GrantFiled: April 25, 2024Date of Patent: July 22, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12349435Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: February 13, 2024Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin