Abstract: A source/drain region is formed for a nanostructure transistor of a semiconductor device such that a hollow cavity extends into the source/drain region from a top of the source/drain region into the source/drain region. In some implementations, the cavity extends fully through the depth of the source/drain region. The cavity results from partial epitaxial growth of one or more epitaxial layers of the source/drain region. A metal core of the source/drain region is formed in the cavity and electrically coupled to a source/drain contact of a nanostructure transistor such that electrically conductive material is recessed within the source/drain region. This provides a greater amount of surface area for the source/drain contact to contact the source/drain region than if the source/drain region were fully filled in with epitaxially-grown semiconductor material.

Abstract: A source/drain contact of a nanostructure transistor is formed such that the source/drain contact is recessed within an underlying source/drain region of the nanostructure transistor using a multiple-step etching process. The source/drain contact being recessed within the source/drain region provides a greater amount of surface area for the source/drain contact to contact the source/drain region. This provides for increased contact surface area between the source/drain contact and the source/drain region, and the increased contact surface area provides for reduced contact resistance between the source/drain region and the source/drain contact, because of the less-restricted current flow path between the source/drain region and the source/drain contact.

Abstract: A source/drain region is formed for a nanostructure transistor of a semiconductor device such that the source/drain region includes a metal core. The metal core provides a greater amount of surface area for a front side source/drain contact and a back side source/drain contact to be coupled to the source/drain region than if the source/drain region were fully filled in with epitaxially-grown semiconductor material. The increased contact surface area provides for reduced contact resistance between the source/drain region and the front side and back side source/drain contacts because of the less-restricted current flow path between the source/drain region and the front side and back side source/drain contacts. The reduced contact resistance between the source/drain region and the front side and back side source/drain contacts enables a greater power efficiency to be achieved for the nanostructure transistor and/or enables increased switching speeds to be achieved for the nanostructure transistor.

Abstract: A semiconductor device is provided. The semiconductor device comprises a detection circuit electrically coupled between a first node and a second node. The semiconductor device comprises a discharge circuit electrically coupled between the first node and a third node. The semiconductor device comprises a biasing circuit electrically coupled between the second node and the third node. The discharge circuit and the biasing circuit are configured to electrically conduct the first node and the second node in response to receiving a first signal from the detection circuit through a fourth node. A first voltage difference exists between the third node and the fourth node.

Abstract: A semiconductor device is provided, including an input/output (I/O) pad, a power clamp, an electrostatic discharge (ESD) clamp circuit, a bias circuit, and a voltage-triggered source. The power clamp is coupled between first and second power rails. The ESD clamp circuit is connected to the I/O pad and coupled between an electrostatic discharge bus and the second power rail. The bias circuit is coupled between the first power rail and the electrostatic discharge bus, and is configured to couple the ESD bus to the first power rail during a normal operation mode, and float the electrostatic discharge bus during an electrostatic discharge mode or a fail-safe mode. The voltage-triggered source is coupled between the ESD bus and the second power rail, and provides a trigger voltage for a first electrostatic discharge path in response to an ESD event occurring on the I/O pad.

Abstract: A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

Abstract: A method for forming a semiconductor structure includes providing an epitaxial structure including a first semiconductor material and a second semiconductor material, depositing a metal-containing structure on the epitaxial structure, and annealing metal-containing structure and the epitaxial structure to form a metal silicide layer. The metal-containing structure includes a first metal layer, a second metal layer and a third metal layer. The first metal layer and the third metal layer include a first metal material. The second metal layer includes a second metal material. The second metal layer is disposed between the first metal layer and the third metal layer. The metal silicide layer includes the first semiconductor material, the second semiconductor material, the first metal material and the second metal material. Each of a concentration of the first metal material and a concentration of the second metal material in the metal silicide layer varies along a thickness direction.

Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first and second node, a discharging circuit coupled between the first and second node, a charging circuit, and a first conductive structure on the back-side of the semiconductor wafer, and extending into the first well and being directly coupled to the first source of the first transistor. The discharging circuit includes a first transistor of a first type in a semiconductor wafer. The first transistor includes a first well, a first gate coupled to the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. a charging circuit coupled to the second node and the third node, and configured to charge the third node during an ESD event at the second node.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit to discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes an epitaxial structure and a metal silicide layer. The epitaxial structure includes a semiconductor material. The metal silicide layer is disposed on the epitaxial structure. The metal silicide layer includes the semiconductor material, a first metal material and a second metal material. An atomic size of the first metal material is greater than an atomic size of the second metal material, and a concentration of the first metal material in the metal silicide layer varies along a thickness direction.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.

Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.