Abstract: A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period.

Abstract: Disclosed are a concurrent selftest engine and its applications to verify, initialize and scramble the system memory concurrently along with mainline operations. In prior art, memory reconfiguration and initialization can only be done by firmware with a full system shutdown and reboot. The disclosed hardware, working along with firmware, allows us to do comprehensive memory test operations on the extended customer memory area while the customer mainline memory accesses arc running in parallel. The hardware consists of concurrent selftest engines and priority logic. Great flexibility is achieved by the new design because customer-usable memory area can be dynamically allocated, verified and initialized. The system performance is improved by the fact that the selftest is hardware-driven whereas in prior art, the firmware drove the selftest. More comprehensive test patterns can be used to improve system memory RAS as well.

Abstract: A power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

Abstract: A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period.

Abstract: Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.

Abstract: Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.