Patents by Inventor Lizabeth Ann Keser
Lizabeth Ann Keser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9171782Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.Type: GrantFiled: August 6, 2013Date of Patent: October 27, 2015Assignee: QUALCOMM IncorporatedInventors: Christine Sung-An Hau-Riege, You-Wen Yau, Kevin Patrick Caffey, Lizabeth Ann Keser, Gene Hyde McAllister, Reynante Tamunan Alvarado, Steve Joseph Bezuk, Damion Bryan Gastelum
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Patent number: 9142434Abstract: Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.Type: GrantFiled: October 23, 2008Date of Patent: September 22, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wei Gao, Craig S. Amrine, Zhiwei Gong, Scott M. Hayes, Lizabeth Ann Keser, George R. Leal, William H. Lytle
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Publication number: 20150228594Abstract: A semiconductor device is provided that has a redistribution layer with reduced resistance. The semiconductor device comprises a plurality of bonding pads on a substrate, a redistribution layer coupled to the bonding pads through a plurality of vias, a dielectric layer over the redistribution layer, that includes an opening that exposes a portion of the redistribution layer. The bonding pads are at least partially under the opening.Type: ApplicationFiled: March 21, 2014Publication date: August 13, 2015Applicant: QUALCOMM INCORPORATEDInventors: Reynante Tamunan Alvarado, Ruey Kae Zang, Lizabeth Ann Keser
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Patent number: 9054111Abstract: An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation.Type: GrantFiled: April 7, 2009Date of Patent: June 9, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jianwen Xu, Lizabeth Ann A. Keser, Goerge R. Leal, Betty H. Yeung
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Publication number: 20150048517Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, Zhongping Bao, Reynante Tamunan Alvarado
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Publication number: 20150041982Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: QUALCOMM IncorporatedInventors: Christine Sung-An Hau-Riege, You-Wen Yau, Kevin Patrick Caffey, Lizabeth Ann Keser, Gene H. McAllister, Reynante Tamunan Alvarado, Steve J. Bezuk, Damion Bryan Gastelum
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Publication number: 20140339712Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.Type: ApplicationFiled: May 20, 2013Publication date: November 20, 2014Applicant: QUALCOMM IncorporatedInventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Jianwen Xu
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Publication number: 20120252169Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Neil T. Tracht, Darrel R. Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Patent number: 8217511Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.Type: GrantFiled: July 31, 2007Date of Patent: July 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Neil T. Tracht, Darrel R Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Publication number: 20110217814Abstract: Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.Type: ApplicationFiled: October 23, 2008Publication date: September 8, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Wei Gao, Craig S. Amrine, Zhiwei Gong, Scott M. Hayes, Lizabeth Ann Keser, George R. Leal, William H. Lytle
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Publication number: 20100252919Abstract: An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation.Type: ApplicationFiled: April 7, 2009Publication date: October 7, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jianwen Xu, Lizabeth Ann Keser, Goerge R. Leal, Betty H. Yeung
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Publication number: 20100148357Abstract: A method (20) of packaging integrated circuit dies (70) includes obtaining (22) a heat spreader substrate (24) having a top surface (38) with cavities (30) formed therein, each of the cavities (30) having a cavity floor (44). A surface (74) of each die (70) is attached (66) to one of the cavity floors (44) such that a surface (72) of each die (70) and the top surface (38) of the substrate (24) are coplanar. Build-up layers (88) with electrical interconnects (97) are formed (86) over the surface (72) of each die (80) and the surface (38) of the substrate (24) to form a panel (68) of IC dies (70). Following formation of the build-up layers (88), the panel (68) is separated (108) into multiple integrated circuit packages (28), each including electrical interconnects (97), a die (70), and the substrate (24) for dissipating heat away from the die (70) during operation.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Liyu Yang, Scott M. Hayes, Lizabeth Ann A. Keser, George R. Leal
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Publication number: 20090032933Abstract: Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventors: Neil T. Tracht, Darrel R. Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
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Publication number: 20080182363Abstract: A method for forming a microelectronic assembly is provided. A carrier substrate (30) is provided. A sacrificial layer (38) is formed over the carrier substrate. A polymeric layer (40), including a polymeric tape (42) and a polymeric layer adhesive (44), is formed over the sacrificial layer. The polymeric layer adhesive is between the sacrificial layer and the polymeric tape. A microelectronic die (52), having an integrated circuit formed therein, is placed on the polymeric layer. The microelectronic die is encapsulated with an encapsulation material (54) to form an encapsulated structure (58). The polymeric layer and the encapsulated structure are separated from the carrier substrate. The separating of the polymeric layer and the encapsulated structure includes at least partially deteriorating the sacrificial layer.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Craig S. Amrine, Owen R. Fay, Lizabeth Ann Keser, Kevin R. Lish, William H. Lytle, Chandrasekaram Ramiah, Jerry L. White
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Patent number: 7405102Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.Type: GrantFiled: June 9, 2006Date of Patent: July 29, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Tien Yu T. Lee, Craig S. Amrine, Victor A. Chiriac, Lizabeth Ann Keser, George R. Leal, Robert J. Wenzel
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Publication number: 20070284711Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Inventors: Tien Yu T. Lee, Craig S. Amrine, Victor A. Chiriac, Lizabeth Ann Keser, George R. Leal, Robert J. Wenzel
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Patent number: 7108755Abstract: A method for preparing a metal surface (34) for a soldering operation is provided. In accordance with the method, the metal surface is treated with a solder flux (31) comprising a supersaturated solution of a carboxylic acid.Type: GrantFiled: July 30, 2002Date of Patent: September 19, 2006Assignee: Motorola, Inc.Inventors: Li Ann Wetz, Lizabeth Ann Keser, Rajiv Bajaj, Treliant Fang
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Patent number: 6930032Abstract: A method for creating an under bump metallization layer (37) is provided. In accordance with the method, a die (33) is provided which has a die pad (35) disposed thereon. A photo-definable polymer (51 or 71) is deposited on the die pad, and an aperture (66) is created in the photo-definable polymer. Finally, an under bump metallization layer (37) is deposited in the aperture. A die package is also provided comprising a die having a die pad (35) disposed thereon, and having an under bump metallization layer (37) disposed on the die pad. The structure has a depression or receptacle (57) therein and has a thickness of at least about 20 microns.Type: GrantFiled: May 14, 2002Date of Patent: August 16, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Vijay Sarihan, Owen Fay, Lizabeth Ann Keser
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Publication number: 20040020562Abstract: A method for preparing a metal surface (34) for a soldering operation is provided. In accordance with the method, the metal surface is treated with a solder flux (31) comprising a supersaturated solution of a carboxylic acid.Type: ApplicationFiled: July 30, 2002Publication date: February 5, 2004Applicant: Motorola Inc.Inventors: Li Ann Wetz, Lizabeth Ann Keser, Rajiv Bajaj, Treliant Fang
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Publication number: 20030214036Abstract: A method for creating an under bump metallization layer (37) is provided. In accordance with the method, a die (33) is provided which has a die pad (35) disposed thereon. A photo-definable polymer (51 or 71) is deposited on the die pad, and an aperture (66) is created in the photo-definable polymer. Finally, an under bump metallization layer (37) is deposited in the aperture. A die package is also provided comprising a die having a die pad (35) disposed thereon, and having an under bump metallization layer (37) disposed on the die pad. The structure has a depression or receptacle (57) therein and has a thickness of at least about 20 microns.Type: ApplicationFiled: May 14, 2002Publication date: November 20, 2003Applicant: Motorola Inc.Inventors: Vijay Sarihan, Owen Fay, Lizabeth Ann Keser