Patents by Inventor Loi N. Nguyen
Loi N. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8853850Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.Type: GrantFiled: March 4, 2013Date of Patent: October 7, 2014Assignee: STMicroelectronics, Inc.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen, Venkata Ramana Yogi Mallela
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Patent number: 8853802Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.Type: GrantFiled: May 31, 2012Date of Patent: October 7, 2014Assignees: STMicroelectronics, Inc., STMicroelectronics Asia Pacific PTE, Ltd.Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
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Patent number: 8680631Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.Type: GrantFiled: April 12, 2013Date of Patent: March 25, 2014Assignee: STMicroelectronics, Inc.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen
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Publication number: 20130228881Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.Type: ApplicationFiled: April 12, 2013Publication date: September 5, 2013Applicant: STMicroelectronics, Inc.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen
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Patent number: 8432006Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.Type: GrantFiled: August 29, 2011Date of Patent: April 30, 2013Assignee: STMicroelectronics, Inc.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen
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Patent number: 8405202Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.Type: GrantFiled: December 31, 2009Date of Patent: March 26, 2013Assignee: STMicroelectronics, Inc.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen, Venkata Ramana Yogi Mallela
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Publication number: 20120235254Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.Type: ApplicationFiled: May 31, 2012Publication date: September 20, 2012Applicants: STMICROELECTRONICS ASIA PACIFIC PTE, LTD., STMICROELECTRONICS, INC.Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
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Patent number: 8193595Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.Type: GrantFiled: December 31, 2009Date of Patent: June 5, 2012Assignees: STMicroelectronics, Inc., STMicroelectronics Asia Pacific Pte Ltd.Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
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Publication number: 20120056281Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.Type: ApplicationFiled: August 29, 2011Publication date: March 8, 2012Applicant: STMICROELECTRONICS, INC.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen
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Patent number: 8022491Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.Type: GrantFiled: June 30, 2009Date of Patent: September 20, 2011Assignee: STMicroelectronics, Inc.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen
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Publication number: 20110156175Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS ASIA PACIFIC PTE LTD.Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
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Publication number: 20110042801Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.Type: ApplicationFiled: December 31, 2009Publication date: February 24, 2011Applicant: STMICROELECTRONICS, INC.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen, Venkata Ramana Yogi Mallela
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Publication number: 20100164024Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.Type: ApplicationFiled: June 30, 2009Publication date: July 1, 2010Applicant: STMICROELECTRONICS, INC.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen
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Patent number: 6472261Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.Type: GrantFiled: March 17, 1999Date of Patent: October 29, 2002Assignee: STMicroelectronics, Inc.Inventor: Loi N. Nguyen
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Publication number: 20020000627Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.Type: ApplicationFiled: March 17, 1999Publication date: January 3, 2002Inventor: LOI N. NGUYEN
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Patent number: 6251713Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.Type: GrantFiled: November 26, 1997Date of Patent: June 26, 2001Assignee: STMicroelectronics, Inc.Inventors: Tsiu Chiu Chan, Loi N. Nguyen
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Patent number: 6093963Abstract: A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules.Type: GrantFiled: October 2, 1997Date of Patent: July 25, 2000Assignee: STMicroelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen, Artur P. Balasinski
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Patent number: 6057604Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.Type: GrantFiled: June 30, 1997Date of Patent: May 2, 2000Assignee: STMicroelectronics, Inc.Inventor: Loi N. Nguyen
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Patent number: 5956615Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.Type: GrantFiled: December 22, 1994Date of Patent: September 21, 1999Assignee: STMicroelectronics, Inc.Inventors: Loi N. Nguyen, Frank R. Bryant
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Patent number: RE36938Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.Type: GrantFiled: August 17, 1998Date of Patent: October 31, 2000Assignee: STMicroelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen