Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A method for forming a contact via in an integrated circuit includes the formation of an aluminum conductive element on an integrated circuit device. A conformal insulating layer is then deposited over the device. Using a masking layer, an anisotropic etch is performed to open a via through the conformal insulating layer. During the anisotropic etch, polymers are created from the resist and etch chemistry and adhere to the sidewalls of the via. A resist developer containing Tetra Methyl Amonium Hydroxide is used to remove the polymers from the via. A contact may now be formed by depositing conductive material into the via.

Abstract: According to the present invention, a method is provided for forming contact vias in an integrated circuit. Initially, a first protective layer is formed on an insulating layer, and an opening is created through the insulating layer where a contact is to be made. A conductive layer is deposited over the protective layer and partially fills the opening, forming a conductive plug in the opening. A second protective layer is then formed over the conductive plug. Portions of the conductive layer which were formed over the first protective layer are removed. During removal of those portions of the conductive layer, the second protective layer protects the conductive plug from damage. The first and second protective layers are then removed, leaving the conductive plug in the opening in the insulating layer. A conductive contact can now be made by depositing a second conductive layer over the conductive plug.

Abstract: A method for forming a contact via in an integrated circuit includes the formation of an aluminum conductive element on an integrated circuit device. A conformal insulating layer is then deposited over the device. Using a masking layer, an anisotropic etch is performed to open a via through the conformal insulating layer. During the anisotropic etch, polymers are created from the resist and etch chemistry and adhere to the sidewalls of the via. A resist developer containing tetramethylammonium hydroxide (TMAX) is used to remove the polymers from the via. A contact may now be formed by depositing conductive material into the via.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A substantially planarizing layer is formed over the interlevel dielectric layer. A photoresist layer is formed and patterned over the planarizing layer. The planarizing layer is etched to form openings exposing selected portions of the interlevel dielectric layer, wherein each opening has substantially the same lateral dimensions. The photoresist and planarizing layers are then removed. The interlevel dielectric layer is etched in the openings to expose portions of the underlying integrated circuit.