Abstract: The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.

Abstract: A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.

Abstract: In an embodiment, a method includes compiling, by a processor, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, privileged and non-privileged access right level execution contexts, or a combination thereof. The method further includes generating, in the compilation phase, instructions in machine language having an exclusive secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.

Abstract: In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.

Abstract: A system including a first port configured to simultaneously couple with a first device and a second device; and a management circuit configured to route a data signal received from a first controller to the first device in response to receiving a first-device direction from the first controller and route the data signal received from the first controller to the second device in response to receiving a second-device direction from the first controller unless an override condition for the management circuit is satisfied.

Abstract: In an embodiment a method for managing access rights of software tasks executed by a processing unit (CPU) using a cache memory containing execution data of the tasks in memory locations, each execution data having an attribute representative of a level of access right of the respective task, includes changing the attributes of the locations of the cache memory when the access rights of at least one task changes and retaining the execution data contained in the locations of the cache memory.

Abstract: In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.

Abstract: A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.

Abstract: In an embodiment a method for managing a low-power mode of an electronic device includes at a first request for transitioning an electronic device to a low-power mode, storing values of a first counter and a second counter of the electronic device on a first edge of a first clock and at a second request for transitioning the electronic device out of the low-power mode calculating a number of periods of a second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge and updating the value of the second counter with a calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.

Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

Abstract: A method for life cycle management of a system-on-chip having functions includes multi-user ownership management listing owners of the functions in a directory, and allocating rights of a function over the life cycle of the system-on-chip, according to a configuration command including identifying the function, identifying a right of ownership or access to the function, and a signature of the owner of the function.

Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

Abstract: The system on chip includes a memory controller adapted to receive transactions containing transaction information defining an access to a memory, the memory controller being configured to store the transaction information in a command register, and to control the access to the memory from the content of the command register. The memory controller includes verification circuitry configured to determine the access to the memory depending on a comparison between the transaction information stored in the command register and a list of special information defining special transactions.

Abstract: A system-on-a-chip includes at least one slave resource, a resource isolation system, and a countermeasure circuit capable of and intended to limit the operation of the system against potential anomalies, and, for the at least one slave resource, a protection circuit configured to block or transmit transactions addressed to the resource depending on access rights of the resource and of the transaction. The protection circuit is configured to generate and directly communicate an alert signal to the countermeasure circuit in the event of a transaction being blocked.

Abstract: A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.

Abstract: The system-on-chip includes at least one master device, at least one slave resource, an interconnection bus including an error notification channel, and a resource isolation system including, for each resource, a protection circuit configured to block or transmit transactions addressed to the resource via the interconnection bus, according to access rights of the resource and the transaction. The protection circuit is capable of generating a notification signal on the error notification channel of the interconnection bus in case of blockage of a transaction.

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.

Abstract: The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.

Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.