Patents by Inventor Loic Pallardy

Loic Pallardy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150143072
    Abstract: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 21, 2015
    Applicant: STMicroelectronics International N.V.
    Inventors: Herve Sibert, Loic Pallardy
  • Publication number: 20150026399
    Abstract: Methods of configuring dynamic memory associated with a processing system, are described. The dynamic memory is configured in a plurality of blocks, the method comprises: a) receiving information relating to a utilisation status of the memory; b) processing the received information to determine at least one first block of the memory that is currently not in use for information storage; and c) configuring the at least one first block to be excluded from an information refresh process.
    Type: Application
    Filed: January 23, 2013
    Publication date: January 22, 2015
    Inventors: Maxime Coquelin, Loic Pallardy
  • Publication number: 20120215975
    Abstract: The invention proposes a method for managing random access memory in a computer system, with said computer system comprising a processor, a first static random access memory, and a second dynamic random access memory, the method comprising the steps of:—receiving at least one instruction to be executed by the processor,—determining a priority level for the execution of the instruction by the processor, and—loading the instruction into the first memory for its execution by the processor if its priority level indicates that it is a high priority instruction, or if not—loading the instruction into the second memory for its execution by the processor.
    Type: Application
    Filed: November 3, 2010
    Publication date: August 23, 2012
    Applicants: ST-ERICSSON SA, ST-ERICSSON (FRANCE) SAS
    Inventors: Michel Catrouillet, Loïc Pallardy