Abstract: An apparatus for recognizing an object in an image includes a preprocessing module configured to receive an image including an object and to output a preprocessed image by performing image enhancement processing on the received image to improve a recognition rate of the object included in the received image; and an object recognition module configured to recognize the object included in the image by inputting the preprocessed image to an input layer of an artificial neural network for object recognition.

Abstract: A computer-implemented apparatus installed and executed in a computer to search an optimal design of a neural processing unit (NPU), a hardware accelerator used for driving a computer-implemented artificial neural network (ANN) is disclosed. The NPU comprises a plurality of blocks connected in a form of pipeline, and the number of the plurality blocks and the number of the layers within each block of the plurality blocks are in need of optimization to reduce hardware resources demand and electricity power consumption of the ANN while maintaining the inference accuracy of the ANN at an acceptable level. The computer-implemented apparatus searches for and then outputs an optimal L value and an optimal C value when a first set of candidate values for a number of layers L and a second set of candidate values for a number of channels C per each layer of the ANN is provided.

Abstract: A mobile artificial neural network device is provided. The mobile artificial neural network device includes a camera configured to output a video of a product at a first frame rate, an AI recognition model configured to recognize a product information by receiving the product video, an artificial neural network processor configured to drive the AI recognition model at a second frame rate, and a display module configured to display the video of the product at the first frame rate and display the product information at the second frame rate.

Abstract: A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.

Abstract: A neural network processing unit (NPU) includes a processing element array, an NPU memory system configured to store at least a portion of data of an artificial neural network model processed in the processing element array, and an NPU scheduler configured to control the processing element array and the NPU memory system based on artificial neural network model structure data or artificial neural network data locality information.

Abstract: A method for programming an activation function is provided. The method includes generating segment data for segmenting the activation function; segmenting the activation function into a plurality of segments using the segment data; and approximating at least one segment of the plurality of segments as a programmable segment. An apparatus for performing the method may include a programmable activation function generator configured to generate segment data for segmenting an activation function; segment the activation function into a plurality of segments using the generated segment data; and approximate at least one segment of the plurality of segments as a programmable segment. By using segment data, various non-linear activation functions, particularly newly proposed or known activation functions with some modifications, can be programmed to be processable in hardware.

Abstract: A neural processing unit (NPU) for testing a component during runtime is provided. The NPU may include a plurality of functional components including a first functional component and a second functional component. At least one of the plurality of functional components may be driven for calculation of an artificial neural network. Another one of the plurality of functional components may be selected as a component under test (CUT). A scan test may be performed on the at least one functional component selected as the CUT. A tester for detecting a defect of an NPU is also provided. The tester may include a component tester configured to communicate with at least one functional component of the NPU, select the at least one functional component as a CUT, and perform a scan test for the selected CUT.

Abstract: An apparatus for recognizing an object in an image includes a preprocessing module configured to receive an image including an object and to output a preprocessed image by performing image enhancement processing on the received image to improve a recognition rate of the object included in the received image; and an object recognition module configured to recognize the object included in the image by inputting the preprocessed image to an input layer of an artificial neural network for object recognition.

Abstract: A computer-implemented apparatus installed and executed in a computer to search an optimal design of a neural processing unit (NPU), a hardware accelerator used for driving a computer-implemented artificial neural network (ANN) is disclosed. The NPU comprises a plurality of blocks connected in a form of pipeline, and the number of the plurality blocks and the number of the layers within each block of the plurality blocks are in need of optimization to reduce hardware resources demand and electricity power consumption of the ANN while maintaining the inference accuracy of the ANN at an acceptable level. The computer-implemented apparatus searches for and then outputs an optimal L value and an optimal C value when a first set of candidate values for a number of layers L and a second set of candidate values for a number of channels C per each layer of the ANN is provided.

Abstract: A neural processing unit of a binarized neural network (BNN) as a hardware accelerator is provided, for the purpose of reducing hardware resource demand and electricity consumption while maintaining acceptable output precision. The neural processing unit may include: a first block configured to perform convolution by using a binarized feature map with a binarized weight; and a second block configured to perform batch-normalization on an output of the first block. A register having a particular size may be disposed between the first block and the second block. Each of the first block and the second block may include one or more processing engines. The one or more processing engines may be connected in a form of pipeline.

Abstract: A control method of an image signal processor for an artificial neural network may be configured to include a step of acquiring an image, a step of determining at least one image characteristic data corresponding to the image, and a step of determining an image correction parameter (SFR preset) for improving an inference accuracy of an artificial neural network model based on the at least one of image characteristic data and an inference accuracy profile of an artificial neural network model.

Abstract: A method for stabilizing an image based on artificial intelligence includes acquiring tremor detection data with respect to the image, the tremor detection data acquired from two or more sensors; outputting stabilization data for compensating for an image shaking, the stabilization data outputted using an artificial neural network (ANN) model trained to output the stabilization data based on the tremor detection data; and compensating for the image shaking using the stabilization data. A camera module includes a lens; an image sensor to output an image captured through the lens; two or more sensors to output tremor detection data with respect to the image; a controller to output stabilization data based on the tremor detection data using an ANN model; and a stabilization unit to compensate for an image shaking using the stabilization data. The ANN model is trained to output the stabilization data based on the tremor detection data.

Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

Abstract: A learning model creation method for performing a specific function for an electronic device, according to an embodiment of the present invention, can include the steps of: preparing big data for training an artificial neural network including, in pairs, sensing data received from a random sensing data generation unit for sensing human behaviors and specific function performance determination data for determining whether to perform a specific function of an electronic device with respect to the sensing data; preparing an artificial neural network model, which includes nodes of an input layer through which the sensing data is inputted, nodes of an output layer through which the specific function performance determination data of the electronic device is outputted, and association parameters between the nodes of the input layer and the nodes of the output layer, and calculates inputs of the sensing data for the nodes of the input layer in order to output the specific function performance determination data from

Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

Abstract: A neural processing unit (NPU), a method for driving an artificial neural network (ANN) model, and an ANN driving apparatus are provided. The NPU includes a semiconductor circuit that includes at least one processing element (PE) configured to process an operation of an artificial neural network (ANN) model; and at least one memory configurable to store a first kernel and a first kernel filter. The NPU is configured to generate a first modulation kernel based on the first kernel and the first kernel filter and to generate second modulation kernel based on the first kernel and a second kernel filter generated by applying a mathematical function to the first kernel filter. Power consumption and memory read time are both reduced by decreasing the data size of a kernel read from a separate memory to an artificial neural network processor and/or by decreasing the number of memory read requests.

Abstract: A neural processing unit (NPU) includes an internal memory storing information on combinations of a plurality of artificial neural network (ANN) models, the plurality of ANN models including first and second ANN models; a plurality of processing elements (PEs) to process first operations and second operations of the plurality of ANN models in sequence or in parallel, the plurality of PEs including first and second groups of PEs; and a scheduler to allocate to the first group of PEs a part of the first operations for the first ANN model and to allocate to the second group of PEs a part of the second operations for the second ANN model, based on an instruction related to information on an operation sequence of the plurality of ANN models or further based on ANN data locality information. The first and second operations may be performed in parallel or in a time division.

Abstract: A trained model creation method for performing a specific function for an electronic device includes preparing big data for training an artificial neural network and specific function performance determination data for determining whether to perform a specific function of an electronic device with respect to the sensing data; and preparing an artificial neural network model, which calculates inputs of the sensing data for the nodes of the input layer in order to output the specific function performance determination data from the nodes of the output layer. The artificial neural network model is trained by repeatedly performing a process of inputting the sensing data included in the prepared big data into the nodes of the input layer and outputting the specific function performance determination data that pairs with the sensing data included in the big data from the nodes of the output layer so as to update the association parameters.

Abstract: A neural processing unit (NPU), a method for driving an artificial neural network (ANN) model, and an ANN driving apparatus are provided. The NPU includes a semiconductor circuit that includes at least one processing element (PE) configured to process an operation of an artificial neural network (ANN) model; and at least one memory configurable to store a first kernel and a first kernel filter. The NPU is configured to generate a first modulation kernel based on the first kernel and the first kernel filter and to generate second modulation kernel based on the first kernel and a second kernel filter generated by applying a mathematical function to the first kernel filter. Power consumption and memory read time are both reduced by decreasing the data size of a kernel read from a separate memory to an artificial neural network processor and/or by decreasing the number of memory read requests.