Abstract: A method performs a plurality of operations on an artificial neural network (ANN). The plurality of operations includes storing in at least one memory a set of weights, at least a portion of a first batch channel of a plurality of batch channels, and at least a portion of a second batch channel of the plurality of batch channels; and calculating the at least a portion of the first batch channel and the at least a portion of the second batch channel by the set of weights. A batch mode, configured to process a plurality of input channels, can determine the operation sequence in which the on-chip memory and/or internal memory stores and computes the parameters of the ANN. Even if the number of input channels increases, processing may be performed with one neural processing unit including a memory configured in consideration of a plurality of input channels.

Abstract: A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.

Abstract: A memory device for an artificial neural network (ANN) includes at least one memory cell array of N columns and M rows; and a memory controller configured to sequentially perform a read or write operation of data of the at least one memory cell array in a burst mode based on predetermined sequential access information. Each of the at least one memory cell array may include a plurality of dynamic memory cells having a leakage current characteristic. The memory device may further include a processor configured to provide the memory controller with the ANN data locality information or information for identifying an input feature map, a kernel, and an output feature map. The memory controller can prepare data of an ANN model processed at a processor-memory level before being requested by the processor, thus enabling a substantial reduction in the delay of memory data being supplied to the processor.

Abstract: The present disclosure provides a method for bit quantization of an artificial neural network. This method may comprise: (a) a step of selecting one parameter or one parameter group to be quantized in an artificial neural network; (b) a bit quantization step of reducing the size of data representation for the selected parameter or parameter group to bits; (c) a step of determining whether the accuracy of the artificial neural network is greater than or equal to a predetermined target value; and (d) a step of, when the accuracy of the artificial neural network is greater than or equal to the target value, repeatedly performing said step (a) to step (c).

Abstract: A memory system of an artificial neural network (ANN) includes a processor configured to process an ANN model; and an ANN memory controller configured to control a rearrangement of data of the ANN model stored in a memory and to operate the data of the ANN model stored in the memory in a read-burst mode based on ANN data locality information of the ANN model. The ANN memory controller may receive pre-generated ANN data locality information, or the processor may generate a plurality of data access requests sequentially so that the ANN memory controller may generate the ANN data locality information by monitoring the plurality of data access requests. The ANN memory controller prepares, based on an artificial neural network data locality, data before receiving a request from the processor in order to reduce a delay in the data supply of the memory to the processor.

Abstract: A system for an artificial neural network (ANN) includes a processor configured to output a memory control signal including an ANN data locality; a main memory in which data of an ANN model corresponding to the ANN data locality is stored; and a memory controller configured to receive the memory control signal from the processor and to control the main memory based on the memory control signal. The memory controller may be further configured to control, based on the memory control signal, a read or write operation of data of the main memory required for operation of the artificial neural network. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

Abstract: A system for an artificial neural network (ANN) includes a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell. The main memory may be configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line. The memory controller may be further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

Abstract: An apparatus for recognizing an object in an image includes a preprocessing module configured to receive an image including an object and to output a preprocessed image by performing image enhancement processing on the received image to improve a recognition rate of the object included in the received image; and an object recognition module configured to recognize the object included in the image by inputting the preprocessed image to an input layer of an artificial neural network for object recognition.

Abstract: The present disclosure provides a bit quantization method of an artificial neural network. This method may include: (a) of selecting one parameter or one parameter group to be quantized in the artificial neural network; (b) a bit quantizing to reduce the data representation size for the selected parameter or parameter group to a unit of bits; (c) of determining whether the accuracy of the artificial neural network is equal to or greater than a predetermined target value; and (d) repeating steps (a) to (c) when the accuracy of the artificial neural network is equal to or greater than the target value.

Abstract: A learning model creation method for performing a specific function for an electronic device, according to an embodiment of the present invention, can include the steps of: preparing big data for training an artificial neural network including, in pairs, sensing data received from a random sensing data generation unit for sensing human behaviors and specific function performance determination data for determining whether to perform a specific function of an electronic device with respect to the sensing data; preparing an artificial neural network model, which includes nodes of an input layer through which the sensing data is inputted, nodes of an output layer through which the specific function performance determination data of the electronic device is outputted, and association parameters between the nodes of the input layer and the nodes of the output layer, and calculates inputs of the sensing data for the nodes of the input layer in order to output the specific function performance determination data from

Abstract: The present disclosure provides a method for bit quantization of an artificial neural network. This method may comprise: (a) a step of selecting one parameter or one parameter group to be quantized in an artificial neural network; (b) a bit quantization step of reducing the size of data representation for the selected parameter or parameter group to bits; (c) a step of determining whether the accuracy of the artificial neural network is greater than or equal to a predetermined target value; and (d) a step of, when the accuracy of the artificial neural network is greater than or equal to the target value, repeatedly performing said step (a) to step (c).

Abstract: Disclosed is a data cache or data management device for caching data between at least one processor and at least one memory, and supporting an artificial neural network (ANN) operation executed by the at least one processor. The data cache device or the data management device can comprise an internal controller for predicting the next data operation request on the basis of ANN data locality of the ANN operation. The internal controller monitors data operation requests associated with the ANN operation from among data operation requests actually made between the at least one processor and the at least one memory, thereby extracting the ANN data locality of the ANN operation.

Abstract: The present disclosure relates to a method for providing shopping information by product and an electronic device performing the same and, more particularly, to a method for providing shopping information by product using an AI recognition model obtained by machine learning of an artificial neural network, and an electronic device performing the same.

Abstract: A method of securing bus architecture from a Trojan attack. A restricted address access detector generates an unauthorized access detection signal when a master ID signal is within a restricted range. The unauthorized access detection signal disables the requested slave select signal, and the address decoder instead outputs a default slave select signal. A counter determines the duration of a lock signal from a master, and a comparator activates a malicious bus lock signal if the lock signal duration exceeds a threshold. The master mask register forcibly gates the lock signal upon receipt of the malicious bus lock signal. If the duration of a wait request from a slave exceeds a maximum duration register value, a comparator activates a malicious wait detection signal to disable the wait request signal. The method might include storing identifying information about the malicious master and storing a slave ID corresponding to the malicious slave.

Abstract: A method of securing bus architecture from a Trojan attack. A restricted address access detector generates an unauthorized access detection, signal when a master ID signal is within a restricted range. The unauthorized access detection signal disables the requested slave select signal, and the address decoder instead outputs a default slave select signal. A counter determines the duration of a lock signal from a master, and a comparator activates a malicious bus lock signal if the lock signal duration exceeds a threshold. The master mask register forcibly gates the lock signal upon receipt of the malicious bus lock signal. If the duration of a wait request from a slave exceeds a maximum duration register value, a comparator activates a malicious wait detection signal to disable the wait request signal. The method might include storing identifying information about the malicious master and storing a slave ID corresponding to the malicious slave.