Patents by Inventor Lokesh M. Gupta

Lokesh M. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10831665
    Abstract: A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a second server, where data in the first cache is also written in the second NVS and data in the second cache is also written in the first NVS. In response to a failure of the first server, a determination is made as to whether space exists in the second NVS to accommodate the data stored in the second cache. In response to determining that space exists in the second NVS to accommodate the data stored in the second cache, the data is transferred from the second cache to the second NVS.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 10831559
    Abstract: Provided are a computer program product, system, and method for managing processor threads of a plurality of processors. In one embodiment, a parameter of performance of the computing system is measured, and the configurations of one or more processor nodes are dynamically adjusted as a function of the measured parameter of performance. In this manner, the number of processor threads being concurrently executed by the plurality of processor nodes of the computing system may be dynamically adjusted in real time as the system operates to improve the performance of the system as it operates under various operating conditions. It is appreciated that systems employing processor thread management in accordance with the present description may provide other features in addition to or instead of those described herein, depending upon the particular application.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10831597
    Abstract: Provided are a computer program product, system, and method for receiving, at a secondary storage controller, information on modified data from a primary storage controller to use to calculate parity data. The secondary storage controller receives from the primary storage controller difference data calculated from modified data and a pre-modified version of the modified data for a primary group of tracks at the primary storage and one of the modified data and new primary parity data calculated at the primary storage controller from the modified data and the difference data. The secondary storage controller uses the difference data and one of the modified data and the new primary parity data to write new secondary parity data and the modified data to a secondary group of tracks at the secondary storage.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, John C. Elliott
  • Patent number: 10834188
    Abstract: Provided are a method, a system, and a computer program product in which metadata associated with data is maintained, wherein the metadata indicates whether storage of the data is restricted geographically. A controller receives a request to store the data in cloud storage comprising a plurality of cloud servers located in a plurality of geographical locations. The controller determines where to store the data in the cloud storage, by interpreting the metadata.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Micah Robison
  • Publication number: 20200348975
    Abstract: A machine learning module receives inputs comprising attributes of a storage controller, wherein the attributes affect allocation of a plurality of resources to a plurality of interfaces. In response to a predetermined number of I/O operations occurring in the storage controller, a generation is made via forward propagation through a plurality of layers of the machine learning module, of an output value corresponding to a number of resources to allocate to an interface. A margin of error is calculated based on comparing the generated output value to an expected output value that is generated from an indication of a predetermined function based at least on a number of I/O operations that are waiting for a resource and a number of available resources. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation, to reduce the margin of error.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Lokesh M. Gupta, Matthew R. Craig, Beth Ann Peterson, Kevin John Ash
  • Publication number: 20200348974
    Abstract: A plurality of interfaces that share a plurality of resources in a storage controller are maintained. In response to an occurrence of a predetermined number of operations associated with an interface of the plurality of interfaces, an input is provided on a plurality of attributes of the storage controller to a machine learning module. In response to receiving the input, the machine learning module generates an output value corresponding to a number of resources of the plurality of resources to allocate to the interface in the storage controller.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Lokesh M. Gupta, Matthew R. Craig, Beth Ann Peterson, Kevin John Ash
  • Publication number: 20200334158
    Abstract: Provided are a computer program product, system, and method for updating a track format table used to provide track format codes for cache control blocks with more frequently accessed track format metadata. A track format table associates track format codes with track format metadata. Each instance of the track format metadata indicates a layout of data in a track. Cache control blocks for tracks in the cache include track format codes associated with the track format metadata of the tracks in the cache. Track format access information indicating accesses of track format metadata not included in the track format table. Track format metadata, indicated in the track format access information that is not in the track format table, is added to the track format table to associate with a track format code based on a number of accesses of the track format metadata indicated in the track format access information.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 22, 2020
    Inventors: Lokesh M. GUPTA, Kyler A. ANDERSON, Kevin J. ASH, Beth A. PETERSON
  • Patent number: 10810304
    Abstract: Provided are a computer program product, system, and method for injecting trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. A specified type of command is processed in application code and, in response, trap code is executed to allocate a trap address range. The specified type of command is executed in the application code. A determination is made as to whether an accessing application accesses the trap address range. At least one of transmitting a notification that the accessing application comprises potentially malicious code, monitoring the execution of the accessing application, and restricting execution of the accessing application is performed in response to determining that the accessing application accessed the trap address range.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Trung N. Nguyen, Micah Robison
  • Patent number: 10809938
    Abstract: In one aspect of the present description, safe data commit scan operations of individual data storage systems of a distributed data storage system may be synchronized to reduce the occurrence of reductions in input/output (I/O) response times. In one embodiment, a set of safe data commit scan operations of the individual data storage systems of a distributed data storage system are synchronously timed to substantially overlap in time within a single synchronized safe data commit scan set interval to reduce or eliminate the occurrences of reductions in input/output response times outside the synchronized safe data commit scan set interval. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Roger G. Hathorn
  • Patent number: 10802930
    Abstract: In response to an occurrence of a failure in a storage controller, an input on a plurality of attributes of the storage controller at a time of occurrence of the failure is provided to a machine learning module. In response to receiving the input, the machine learning module generates a plurality of output values corresponding to a plurality of recovery mechanisms to recover from the failure in the storage controller. A recovery is made from the failure in the storage controller, by applying a recovery mechanism whose output value is greatest among the plurality of output values that are generated by the machine learning module.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta
  • Patent number: 10795602
    Abstract: A computer-implemented method according to one embodiment includes, for each portion of data in a write cache: determining whether a given portion of data was added to the write cache prior to completion of a most recent flash copy operation. In response to determining that the given portion of data was not added to the write cache prior to completion of a most recent flash copy operation, a determination is made of whether the given portion of data has a clock bit value corresponding thereto. In response to determining that the given portion of data does not have a clock bit value corresponding thereto, a clock bit value calculated for the given portion of data based on a current amount of unused storage capacity in the write cache. Moreover, in response to determining that the given portion of data has a clock bit value corresponding thereto, it is decremented.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin John Ash, Matthew G. Borlick
  • Patent number: 10783049
    Abstract: In one embodiment, virtual storage drives are allocated to RAID arrays so that no two virtual storage drives of a RAID array are mapped to the same physical storage drive. In another aspect, error handling routines are limited to virtual storage drives impacted by an error in a physical storage drive so that virtual storage drives of the physical storage drive not impacted by the error are bypassed. In yet another aspect, cache operations to a target virtual storage drive may be throttled as a function of both a limit imposed on cache operations directed to the RAID array to which the virtual storage drive is allocated, and a separate limit on cache operations directed to a group of virtual storage drives which are mapped to the same physical storage drive as the target virtual storage drive. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Kevin J. Ash, Karl A. Nielsen
  • Patent number: 10783087
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to select one of multiple cache eviction algorithms to use to evict a track from the cache. A first cache eviction algorithm determines tracks to evict from the cache. A second cache eviction algorithm determines tracks to evict from the cache, wherein the first and second cache eviction algorithms use different eviction schemes. At least one machine learning module is executed to produce output indicating one of the first cache eviction algorithm and the second cache eviction algorithm to use to select a track to evict from the cache. A track is evicted that is selected by one of the first and second cache eviction algorithms indicated in the output from the at least one machine learning module.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Publication number: 20200293447
    Abstract: Provided are a computer program product, system, and method for destaging metadata tracks from cache A counter for a metadata track is updated in response to modifying the metadata track in the cache, wherein there are counters for metadata tracks in the cache. The metadata track is destaged from the cache in response to the counter for the metadata track being less than a threshold value. The counter for the metadata track is decremented based on a number of modified metadata tracks in the cache.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick
  • Patent number: 10776013
    Abstract: Provided are a computer program product, system, and method for performing workload balancing of tracks in storage areas assigned to processing units. For each processing unit, there is an assignment of a storage area of tracks in the storage to the processing unit, at least one queue having I/O requests to the storage area, and queue usage information indicating a quantity related to the I/O requests in the at least one queue. A determination is made from the queue usage information whether to perform workload balancing for a source processing unit having at least one source queue. A target processing unit is selected in response to determining to perform the workload balancing for the source processing unit. Tracks in a source storage area assigned to the source processing unit are moved to a target storage area assigned to the target processing unit.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, John C. Elliott
  • Patent number: 10768822
    Abstract: A method for increasing effective storage capacity in a heterogeneous storage array is disclosed. In one embodiment, such a method determines a number of smaller-capacity storage drives and a number of larger-capacity storage drives in a storage array. The method further determines which RAID arrays in the storage array may be composed exclusively of the larger-capacity storage drives. Using this information, the method establishes a first set of RAID arrays in the storage array that will be composed exclusively of the larger-capacity storage drives and a second set of RAID arrays that may contain the smaller-capacity storage drives. The method then initiates a process to swap the smaller-capacity storage drives in the first set with the larger-capacity storage drives in the second set until the first set of RAID arrays is composed exclusively of the larger-capacity storage drives. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Karl A. Nielsen, Matthew G. Borlick, Kevin J. Ash
  • Publication number: 20200278909
    Abstract: Provided are a method, system, and computer program product in which a storage controller receives a first write command with a first token over a first interface from a host computational device. In response to a failure of the first write command in the storage controller, the storage controller retains selected resources for reuse for a retry of the first write command, wherein the retry of the first write command is expected from the host computational device over a second interface that is a slower communication link than the first interface. In response to receiving, by the storage controller, a second write command with a second token over the second interface, wherein the second token is identical to the first token, the storage controller determines that the second write command is a retry of the first write command and reuses the retained selected resources for executing the second write command.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Inventors: Beth A. Peterson, Kevin J. Ash, Lokesh M. Gupta, Chung M. Fung
  • Publication number: 20200278809
    Abstract: A host computational device transmits a first write command with a first token over a first interface to a storage controller. In response to receiving an indication by the host computational device that the first write command has failed in the storage controller, the host computational device transmits a second write command with a second token over a second interface to the storage controller, wherein the second write command is a retry of the first write command that failed, wherein the second token is identical to the first token, and wherein the second interface is a slower communication link than the first interface.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Inventors: Beth A. Peterson, Kevin J. Ash, Lokesh M. Gupta, Chung M. Fung
  • Patent number: 10761744
    Abstract: Provided are techniques for synchronously performing commit records operations. A local copy of a commit records message is built for a Non-Volatile Storage (NVS) track, with a valid indicator set to indicate that this commit records message is valid and has not been processed yet. A Direct Memory Access (DMA) chain is executed to transfer customer data from a host to real segments and alternate segments of a track buffer and to transfer the local copy of the commit records message to a mail message structure of a mail message array. At DMA completion, an NVS manager is synchronously called to perform a commit records operation with the commit records message in the mail message structure. In response to the commit records operation completing, there is an indication that a new write DMA is allowed to proceed for the NVS track.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson, Louis A. Rasor
  • Patent number: 10754780
    Abstract: Provided area computer program product, system, and method for maintaining track format metadata for target tracks in a target storage in a copy relationship with source tracks in a source storage. Upon receiving a request to a requested target track in the target storage, the source track for the requested target track is staged from the source storage to a cache to be used as the requested target track in response to determining that the copy relationship information indicates that a source track needs to be copied to the requested target track. A determination is made of track format metadata for the requested target track, comprising the staged source track, indicating a format and layout of data in the requested target track and a track format code identifying the track format metadata. The track format code is included in a cache control block for the requested target track.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta