Patents by Inventor Lokesh M. Gupta

Lokesh M. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210072918
    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Brian A. Rinaldi, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210073050
    Abstract: A method is disclosed to reduce lock contention in a data storage system. The method dispatches, on a first processor core, a task configured to acquire a lock on a data storage resource, such as memory. The method then determines whether the first processor core is associated with the data storage resource. If the first processor core is not associated with the data storage resource, the method re-dispatches the task on a second processor core that is associated with the data storage resource. In certain embodiments, the task is only re-dispatched on the second processor core if an amount of effort required to acquire the lock is above a selected threshold. If, on the other hand, the first processor core is associated with the data storage resource, the method executes the task on the first processor core. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: International Business Machines Corporation
    Inventors: Clint A. Hardy, Lokesh M. Gupta, Trung N. Nguyen, Seamus Burke
  • Publication number: 20210073090
    Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Matthew G. Borlick, Sean Patrick Riley, Brian Anthony Rinaldi, Trung N. Nguyen, Lokesh M. Gupta
  • Publication number: 20210073136
    Abstract: A method to dynamically optimize utilization of data transfer techniques includes processing multiple I/O requests using one of several data transfer techniques depending on which data transfer technique is more efficient. The data transfer techniques include: a memory copy data transfer technique that copies cache segments associated with an I/O request from a cache memory to a permanently mapped memory; and a memory mapping data transfer technique that temporarily maps cache segments associated with an I/O request. In order to process the I/O requests, the method utilizes a first number of “copy” windows associated with the memory copy data transfer technique, and a second number of “mapping” windows associated with the memory mapping data transfer technique. The method dynamically adjusts one or more of the first number and the second number to optimize the processing of the I/O requests. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Brian A. Rinaldi
  • Patent number: 10942857
    Abstract: A method to dynamically optimize utilization of data transfer techniques includes processing multiple I/O requests using one of several data transfer techniques depending on which data transfer technique is more efficient. The data transfer techniques include: a memory copy data transfer technique that copies cache segments associated with an I/O request from a cache memory to a permanently mapped memory; and a memory mapping data transfer technique that temporarily maps cache segments associated with an I/O request. In order to process the I/O requests, the method utilizes a first number of “copy” windows associated with the memory copy data transfer technique, and a second number of “mapping” windows associated with the memory mapping data transfer technique. The method dynamically adjusts one or more of the first number and the second number to optimize the processing of the I/O requests. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Brian A. Rinaldi
  • Patent number: 10929034
    Abstract: Stage task control blocks (TCB) are allocated for performing staging operations in a storage controller controlling one or more storage ranks. Destage TCBs are allocated for performing destaging operations in the storage controller. The storage controller adjusts how many stage TCBs and destage TCBs are to be allocated based on response times of the one or more storage ranks.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 10929037
    Abstract: A method for converting a redundant array of independent disks (RAID) to a more robust RAID level is disclosed. Such a method identifies, in a data storage environment, higher risk storage drives having a failure risk above a first threshold. The method determines a number of the higher risk storage drives that are contained within a RAID array of the data storage environment. The method determines whether the number exceeds a second threshold. The method also determines whether a destage rate associated with the RAID array is below a third threshold. In the event the number exceeds the second threshold and the destage rate is below the third threshold, the method converts the RAID array to a more robust RAID level. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 15, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Brian A. Rinaldi
  • Patent number: 10929057
    Abstract: Provided are techniques for selecting a disconnect from different types of channel disconnects using a machine learning module. An Input/Output (I/O) operation is received from a host via a channel. Inputs are provided to a machine learning module. An output is received from the machine learning module. Based on the output, one of no disconnect from the channel, a logical disconnect from the channel, or a physical disconnect from the channel is selected.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Beth A. Peterson, Lokesh M. Gupta, Matthew R. Craig, Kevin J. Ash
  • Publication number: 20210049108
    Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Lokesh M. GUPTA, Kyler A. ANDERSON, Kevin J. ASH, Matthew J. KALOS
  • Publication number: 20210049109
    Abstract: Provided are a computer program product, system, and method for managing adding of accessed tracks to a cache list based on accesses to different regions of the cache list. A cache has a least recently used (LRU) end and a most recently used (MRU) end. A determination is made of a high access region of tracks from the MRU end of the cache list based on a number of accesses to the tracks in the high access region. A flag is set for an accessed track, indicating to indicate the accessed track at the MRU end upon processing the accessed track at the LRU end, in response to the determining the accessed track is in the high access region. After the setting the flag, the accessed track remains at a current position in the cache list before being accessed.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Lokesh M. GUPTA, Kyler A. ANDERSON, Kevin J. ASH, Matthew J. KALOS
  • Publication number: 20210042241
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors. A plurality of insertion points to a cache list for the shared cache having a least recently used (LRU) end and a most recently used (MRU) end identify tracks in the cache list. For each processor, of a plurality of processors, for which indication of tracks accessed by the processor is received, a determination is made of insertion points of the provided insertion points at which to indicate the tracks for which indication is received. The tracks are indicated at positions in the cache list with respect to the determined insertion points.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210042231
    Abstract: Provide a computer program product, system, and method for adjusting insertion points used to determine locations in a cache list at which to indicate tracks based on number of tracks added at insertion points. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end. Each insertion point of the insertion points identifies a track in the cache list. A plurality of tracks are indicated at positions in the cache list with respect to insertion points. For each track indicated at an insertion point of the insertion points, at least one insertion point counter for at least one insertion point with respect to the insertion point at which the track is indicated is incremented. A plurality of the insertion points are adjusted to point to different tracks in the cache list based on insertion point counters for the insertion points.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210042230
    Abstract: Provided are a computer program product, system, and method for maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache. A plurality of insertion points to a cache list for the cache each identify a track in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list that are to be indicated at the MRU end of the cache list. Indication is made of cache hits for each of the insertion points used to indicate locations in the cache list for tracks accessed while indicated in the cache list. The cache hits indicated for the insertion points are to indicate whether to increase or decrease a size of the cache.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210042242
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to move processed tracks. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end, wherein each insertion point of the insertion points identifies a track in the cache list. An insertion point of the insertion points is determined at which to move the processed track in response to determining that a processed track is indicated to move to the MRU end. The processed track is indicated at a position in the cache list with respect to the determined insertion point.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210042229
    Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 10915462
    Abstract: Provided are techniques for destaging pinned retryable data in cache. A ranks scan structure is created with an indicator for each rank of multiple ranks that indicates whether pinned retryable data in a cache for that rank is destageable. A cache directory is partitioned into chunks, wherein each of the chunks includes one or more tracks from the cache. A number of tasks are determined for the scan of the cache. The number of tasks are executed to scan the cache to destage pinned retryable data that is indicated as ready to be destaged by the ranks scan structure, wherein each of the tasks selects an unprocessed chunk of the cache directory for processing until the chunks of the cache directory have been processed.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 10901793
    Abstract: Provided are a computer program product, system, and method for determining whether to process a host request using a machine learning module. Information that relates to at least one of running tasks, mail queue messages related to host requests, Input/Output (I/O) request processing, and a host request received from the host system is provided to a machine learning module. An output representing a processing load in a system is received from the machine learning module. The output is used to determine whether to process the host request.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew R. Craig, Beth A. Peterson, Lokesh M. Gupta, Kevin J. Ash
  • Patent number: 10901916
    Abstract: Provided are a computer program product, system, and method for managing adding of accessed tracks to a cache list based on accesses to different regions of the cache list. A cache has a least recently used (LRU) end and a most recently used (MRU) end. A determination is made of a high access region of tracks from the MRU end of the cache list based on a number of accesses to the tracks in the high access region. A flag is set for an accessed track, indicating to indicate the accessed track at the MRU end upon processing the accessed track at the LRU end, in response to the determining the accessed track is in the high access region. After the setting the flag, the accessed track remains at a current position in the cache list before being accessed.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 10901904
    Abstract: In response to an end of track access for a track in a cache, a determination is made as to whether the track has modified data and whether the track has one or more holes. In response to determining that the track has modified data and the track has one or more holes, an input on a plurality of attributes of a computing environment in which the track is processed is provided to a machine learning module to produce an output value. A determination is made as to whether the output value indicates whether one or more holes are to be filled in the track. In response to determining that the output value indicates that one or more holes are to be filled in the track, the track is staged to the cache from a storage drive.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 10891227
    Abstract: Provided are a computer program product, system, and method for determining modified tracks to destage during a cache scan. A cache scan is initiated at a time interval to determine modified tracks to destage from a cache to the first or second storage. A modified track is processed during the cache scan. The modified track is destaged to the first storage in response to the modified track stored in the first storage. A determination is made as to whether there was a host write to the second storage since a previous cache scan in response to the modified track stored in the second storage. The modified track is destaged to the second storage in response to determining that there was a host write to the second storage since the previous cache scan.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Warren K. Stanley, Edward H. Lin, Kevin J. Ash, Matthew G. Borlick, Kyler A. Anderson