Patents by Inventor Lokesh M. Gupta

Lokesh M. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210224199
    Abstract: A method for improving cache hit ratios for selected storage elements within a storage system includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method periodically scans the first LRU list for non-favored storage elements that have changed to favored storage elements, and the second LRU list for favored storage elements that have changed to non-favored storage elements. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: January 20, 2020
    Publication date: July 22, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11068417
    Abstract: A computational device receives an indication of a minimum retention time in a cache for a plurality of tracks of an application. In response to determining that tracks of the application that are stored in the cache exceed a predetermined threshold in the cache, the computational device demotes one or more tracks of the application from the cache even though a minimum retention time in cache has been indicated for the one or more tracks of the application, while performing least recently used (LRU) based replacement of tracks in the cache.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Roger G. Hathorn, Joseph Hayward, Matthew G. Borlick
  • Patent number: 11068418
    Abstract: Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M Gupta, Trung N. Nguyen
  • Patent number: 11068415
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to move processed tracks. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end, wherein each insertion point of the insertion points identifies a track in the cache list. An insertion point of the insertion points is determined at which to move the processed track in response to determining that a processed track is indicated to move to the MRU end. The processed track is indicated at a position in the cache list with respect to the determined insertion point.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11068413
    Abstract: A computational device receives an indication of minimum retention times in a cache for a plurality of tracks for applications. In response to determining that a first type of application has not specified a maximum percentage of cache for allocation to the first type of application, the maximum percentage of cache for allocation to the first type of application is set to a default value. In response to determining that a second type of application has not specified a maximum percentage of cache for allocation to the second type of application, an entirety of the cache or a percentage of the cache that is greater than the default value is allocated for the second type of application. A least recently used based replacement of tracks is performed in the cache while attempting to satisfy the minimum retention times and the maximum percentage of cache that are allocated.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Roger G. Hathorn, Joseph Hayward, Matthew G. Borlick
  • Patent number: 11062232
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache using a machine learning module. Performance attributes of system components affected by staging tracks from the storage to the cache are provided to a machine learning module. An output is received, from the machine learning module having processed the provided performance attributes, indicating a staging strategy indicating sectors of a track to stage into the cache comprising one of a plurality of staging strategies. Sectors of an accessed track that is not in the cache are staged into the cache according to the staging strategy indicated in the output.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11061826
    Abstract: A minimum retention time in cache is indicated for a first plurality of tracks, where no minimum retention time is indicated for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Joseph Hayward, Matthew G. Borlick
  • Patent number: 11061784
    Abstract: Provided are a computer program product, system, and method for monitoring correctable errors on a bus interface to determine whether to redirect traffic to another bus interface. A processing unit sends Input/Output (I/O) requests from a host to a storage over a first bus interface to a first device adaptor, wherein the first device adaptor provides a first connection to the storage. A determination is made as to whether a number of correctable errors on the first bus interface exceeds an error threshold. The correctable errors are detected and corrected in the first bus interface by hardware of the first bus interface. In response to determining that the number of correctable errors on the first bus interface exceeds the error threshold, at least a portion of I/O requests are redirected to use a second bus interface to connect to a second device adaptor providing a second connection to the storage.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 11055234
    Abstract: Provided are a computer program product, system, and method for managing cache segments between a global queue and a plurality of local queues by training a machine learning module. A machine learning module is provided input comprising cache segment management information related to management of segments in the local queues by the processing units and accesses of the global queue to transfer cache segments between the local queues and the global queue to output an optimum number parameter comprising an optimum number of segments to maintain in a local queue and a transfer number parameter comprising a number of cache segments to move between a local queue and the global queue. The machine learning module is retrained based on the cache segment management information to output an adjusted transfer number parameter and an adjusted optimum number parameter for the processing units.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew R. Craig
  • Patent number: 11054994
    Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Clint A. Hardy, Karl A. Nielsen
  • Patent number: 11055013
    Abstract: A computer-implemented method, according to one embodiment, includes: in response to experiencing a loss of data at a first track of a source volume, determining whether a copy of the lost data has been stored at a second track of a target volume. Moreover, in response to determining that a copy of the lost data has been stored at a second track of the target volume, determine whether the copy of the lost data has been altered since being stored at the second track of the target volume. In response to determining that the copy of the lost data has not been altered since being stored at the second track of the target volume, a request for the copy of the lost data is sent to the target volume. In response, the copy of the lost data is received, and used to recover the lost data.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11048667
    Abstract: A method for improving asynchronous data replication between a primary storage system and a secondary storage system is disclosed. In one embodiment, such a method includes monitoring, in a cache of the primary storage system, unmirrored data elements needing to be mirrored, but that have not yet been mirrored, from the primary storage system to the secondary storage system. The method maintains an LRU list designating an order in which data elements are demoted from the cache. The method determines whether a data element at an LRU end of the LRU list is an unmirrored data element. In the event the data element at the LRU end of the LRU list is an unmirrored data element, the method moves the data element to an MRU end of the LRU list. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 29, 2021
    Assignees: International Business, Machines Corporation
    Inventors: Gail Spear, Lokesh M. Gupta, Kevin J. Ash, David B. Schreiber, Kyler A. Anderson
  • Patent number: 11048641
    Abstract: Provided are a computer program product, system, and method for managing cache segments between a global queue and a plurality of local queues using a machine learning module. Cache segment management information related to management of segments in the local queues and accesses to the global queue to transfer cache segments between the local queues and the global queue, are provided to a machine learning module to output an optimum number parameter comprising an optimum number of segments to maintain in a local queue and a transfer number parameter comprising a number of cache segments to transfer between a local queue and the global queue. The optimum number parameter and the transfer number parameter are sent to a processing unit having a local queue to cause the processing unit to transfer the transfer number parameter of cache segments between the local queue to the global queue.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew R. Craig
  • Patent number: 11049570
    Abstract: A method for dynamically altering a writes-per-day classification of multiple storage drives is disclosed. In one embodiment, such a method monitors, within a storage environment, an amount of overprovisioning utilized by multiple storage drives. Each storage drive has a writes-per-day classification associated therewith. Based on the amount of overprovisioning, the method periodically modifies the writes-per-day classification of the storage drives. The method then reorganizes the storage drives within various storage groups (e.g., RAID arrays, storage tiers, workloads, etc.) based on their writes-per-day classification. For example, the method may place, as much as possible, storage drives of the same writes-per-day classification within the same storage groups. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Micah Robison
  • Patent number: 11048631
    Abstract: Provided are a computer program product, system, and method for maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache. A plurality of insertion points to a cache list for the cache each identify a track in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list that are to be indicated at the MRU end of the cache list. Indication is made of cache hits for each of the insertion points used to indicate locations in the cache list for tracks accessed while indicated in the cache list. The cache hits indicated for the insertion points are to indicate whether to increase or decrease a size of the cache.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11042636
    Abstract: Provided are a computer program product, system, and method for detecting potentially malicious code in a host system accessing data from a storage. A trap storage unit is configured for data in the storage and the trap storage unit is indicated as a trap. Storage units are configured for data in the storage that are not indicated as a trap. A request is received to access the trap storage unit from a process executing in a host system. Notification is returned to the host system that the process requesting to access the trap storage unit is a potentially malicious process.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
  • Publication number: 20210182396
    Abstract: Provided are a computer program product, system, and method for determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. Trap code is executed in response to processing a specified type of command in application code to allocate a trap address range used to detect potentially malicious code. A determination is whether to modify a frequency of executing the trap code in response to processing a specified type of command. The frequency of executing the trap code is modified in response to processing the specified type of command in response to determining to determining to modify the frequency of executing the trap code.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 17, 2021
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Trung N. Nguyen, Micah Robison
  • Patent number: 11036635
    Abstract: Provided are a computer program product, system, and method for selecting resources to make available in local queues for processors to use. Each processor of a plurality of processors maintains a queue of resources for the processor to use when needed for processor operations. One of processors is selected. The selected processor accesses at least one available resource and includes the accessed at least one resource in the queue of the selected processor.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 11036641
    Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks demoted from cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Publication number: 20210173752
    Abstract: Provided are a computer program product, system, and method for recovering storage devices in a storage array having errors. A determination is made to replace a first storage device in a storage array with a second storage device. The storage array is rebuilt by including the second storage device in the storage array and removing the first storage device from the storage array resulting in a rebuilt storage array. The first storage device is recovered from errors that resulted in the determination to replace. Data is copied from the second storage device included in the rebuilt storage array to the first storage device. The recovered first storage device is swapped into the storage array to replace the second storage device in response to copying the data from the second storage device to the first storage device.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 10, 2021
    Inventors: Brian J. Cagno, John C. Elliott, Matthew G. Borlick, Will A. Wright, Lokesh M. Gupta