Patents by Inventor Long Chang

Long Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programming method, reading method and operating system for memory
    Patent number: 9286158
    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 15, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Hsin Liu, Su-Chueh Lo, Kuen-Long Chang, Ken-Hui Chen, Chun-Hsiung Hung
  • CIRCUIT FOR VOLTAGE DETECTION AND PROTECTION AND OPERATING METHOD THEREOF
    Publication number: 20160064921
    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • Memory device and read operation method thereof
    Patent number: 9275695
    Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 1, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hung Chang, Chia-Jung Chen, Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang
  • Handle wafer for high resistivity trap-rich SOI
    Patent number: 9269591
    Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alex Kalnitsky, Chung-Long Chang, Yung-Chih Tsai, Tsung-Yu Yang, Keng-Yu Chen, Yong-En Syu
  • STABILIZATION OF OUTPUT TIMING DELAY
    Publication number: 20160049925
    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Applicant: Macronix International Co., Ltd.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • METHOD AND DEVICE FOR MONITORING DATA ERROR STATUS IN A MEMORY
    Publication number: 20160041861
    Abstract: A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.
    Type: Application
    Filed: January 14, 2015
    Publication date: February 11, 2016
    Inventors: Kuen Long CHANG, Ken Hui CHEN, Su Chueh LO, Chia-Feng CHENG
  • RETENTION LOGIC FOR NON-VOLATILE MEMORY
    Publication number: 20160027522
    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 28, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHUN-HSIUNG HUNG, NAI-PING KUO, KUEN-LONG CHANG, KEN-HUI CHEN, YU-CHEN WANG
  • Method and apparatus for reducing erase disturb of memory by using recovery bias
    Patent number: 9245644
    Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: January 26, 2016
    Assignee: Macronix International Co., Ltd
    Inventors: Chun-Hsiung Hung, Bo-Chang Wu, Kuen-Long Chang, Ken-Hui Chen
  • Mechanisms for forming radio frequency (RF) area of integrated circuit structure
    Patent number: 9230988
    Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: January 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yu Cheng, Keng-Yu Chen, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao
  • SELF-BALANCING VEHICLE FRAME
    Publication number: 20150353158
    Abstract: A self-balancing vehicle frame includes two side frame units and a bearing unit interconnecting the side frame units such that each of the side frame units can tilt independently against the other of the side frame units. Each of side frames is mounted with a wheel, a driver, and a self-balancing electric system integrated with a pedal and handle. Through operation of hands and feet, each of the side frame units is operable to tilt the corresponding components forwardly and rearwardly. As such, a user can operate the vehicle using hands and/or feet to control travelling and turning of the vehicle.
    Type: Application
    Filed: November 14, 2014
    Publication date: December 10, 2015
    Inventor: Fu-Long CHANG
  • Method and system for operating memory
    Patent number: 9208842
    Abstract: A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 8, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Ken-Hui Chen, Kuen-Long Chang, Yu-Chen Wang, Chin-Hung Chang, Chia-Feng Cheng, Min-Hsiung Meng
  • MEMORY DEVICE WITH VARIABLE STROBE INTERFACE
    Publication number: 20150340071
    Abstract: A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 26, 2015
    Inventors: Ken-Hui CHEN, Kuen Long CHANG, Chin-Hung CHANG
  • INPUT PIN CONTROL
    Publication number: 20150323946
    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang, Chao-Hsin Lin
  • Method and apparatus for the erase suspend operation
    Patent number: 9183937
    Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ken-Hui Chen, Chun-Hsiung Hung, Kuen-Long Chang
  • CONFIGURABLE CLOCK INTERFACE DEVICE
    Publication number: 20150293556
    Abstract: A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.
    Type: Application
    Filed: July 31, 2014
    Publication date: October 15, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: KUEN-LONG CHANG, KEN-HUI CHEN, CHANG-TING CHEN
  • DEVICES AND OPERATION METHODS FOR CONFIGURING DATA STROBE SIGNAL IN MEMORY DEVICE
    Publication number: 20150286405
    Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.
    Type: Application
    Filed: April 2, 2015
    Publication date: October 8, 2015
    Inventors: Kuen-Long CHANG, Ken-Hui CHEN, Chang-Ting CHEN
  • Retention logic for non-volatile memory
    Patent number: 9147501
    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: September 29, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang
  • HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI
    Publication number: 20150270143
    Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Inventors: Alex Kalnitsky, Chung-Long Chang, Yung-Chih Tsai, Tsung-Yu Yang, Keng-Yu Chen, Yong-En Syu
  • Lateral double-diffused metal oxide semiconductor
    Patent number: 9142671
    Abstract: The invention provides a lateral double-diffused metal oxide semiconductor (LDMOS). The pre-metal dielectric layer (PMD) of the LDMOS is a silicon rich content material. Additionally, the inter-layer dielectric layer (ILD), inter-metal dielectric layer (IMD), or protective layer of the LDMOS may be formed of a silicon rich content material.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: September 22, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Kwang-Ming Lin, Ming-Cheng Lin, Yu-Long Chang
  • Stacked antenna
    Patent number: 9142886
    Abstract: A stacked antenna includes a first dielectric substrate, a second dielectric substrate, at least one vertical conductive structure, at least one transmission line structure, a driven element, at least one reflector and a director. The second dielectric substrate is stacked on the first dielectric substrate. The conductive structure penetrates the first dielectric substrate or the second dielectric substrate. The transmission line structure is disposed between the first and second dielectric substrates. The driven element is disposed between the first and second dielectric substrates and is electrically connected to the conductive structure through the transmission line structure. The reflector is spaced from the driven element by the first dielectric substrate and is disposed under the first dielectric substrate. The director is spaced from the driven element by the second dielectric substrate.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: September 22, 2015
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Chia Lu, Chen-Fang Tai, Yi-Long Chang