Patents by Inventor Long Chang

Long Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR STRUCTURE WITH ULTRA THICK METAL AND MANUFACTURING METHOD THEREOF
    Publication number: 20170098606
    Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: CHEN-FA LU, CHENG-YUAN TSAI, CHING-CHUNG HSU, CHUNG-LONG CHANG
  • MEMORY DEVICE WITH FLEXIBLE DATA TRANSFER RATE INTERFACE AND METHOD THEREOF
    Publication number: 20170083439
    Abstract: A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Kuen-Long CHANG, Su-Chuch LO, Chao Hsin LIN, Ken-Hui CHEN
  • Mechanisms for forming radio frequency (RF) area of integrated circuit structure
    Patent number: 9589831
    Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yu Cheng, Keng-Yu Chen, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao
  • ELECTRONIC DEVICE AND DATA EXCHANGE METHOD INCLUDING PROTOCOL INDICATIVE OF MODES OF OPERATION
    Publication number: 20170060785
    Abstract: An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus.
    Type: Application
    Filed: April 20, 2016
    Publication date: March 2, 2017
    Inventors: Kuen Long CHANG, Yu Chen WANG, Ken Hui CHEN
  • Power source for memory circuitry
    Patent number: 9536575
    Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: January 3, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wu-Chin Peng, Chun-Yi Lee, Ken-Hui Chen, Kuen-Long Chang, Chun Hsiung Hung
  • ECC method for flash memory
    Patent number: 9535785
    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 3, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Nai-Ping Kuo, Shih-Chang Huang, Chin-Hung Chang, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Monitoring data error status in a memory
    Patent number: 9519539
    Abstract: A method for outputting data error status of a memory device includes generating data status indication codes indicating error status of data chunks transmitted by a memory controller, and combining the data status indication codes with corresponding data chunks to generate an output signal, and outputting the output signal to a data bus pin.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: December 13, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen Long Chang, Ken Hui Chen, Su Chueh Lo, Chia-Feng Cheng
  • Method and device for processing serial binary input by comparing binary digits at even and odd locations of the input
    Patent number: 9514088
    Abstract: A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: December 6, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Ken Hui Chen, Kuen Long Chang, Yu Chen Wang
  • Method for reducing noise and computer program thereof and electronic device
    Patent number: 9514765
    Abstract: A method for reducing noise is used to divide a received voice into plural voice segments and set a predetermined energy value. The energy of voice segment which is higher than the predetermined energy value is determined as normal voice and outputs directly, and the energy of voice segment which is lower than the predetermined energy value is determined as noise and will be processed.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 6, 2016
    Assignee: UNLIMITER MFA CO., LTD.
    Inventors: Kuan-Li Chao, Chih-Long Chang, Ju-Huei Tsai, Jing-Wei Li, Wei-Ming Chen, Neo Bob Chih-Yung Young, Kuo-Ping Yang
  • Retention logic for non-volatile memory
    Patent number: 9514834
    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: December 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang
  • Method and apparatus for reducing erase time of memory by using partial pre-programming
    Patent number: 9502121
    Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: November 22, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Yi Lee, Kuen-Long Chang, Chun-Hsiung Hung
  • Self-balancing vehicle frame
    Patent number: 9499228
    Abstract: A self-balancing vehicle frame includes two side frame units and a bearing unit interconnecting the side frame units such that each of the side frame units can tilt independently against the other of the side frame units. Each of side frames is mounted with a wheel, a driver, and a self-balancing electric system integrated with a pedal and handle. Through operation of hands and feet, each of the side frame units is operable to tilt the corresponding components forwardly and rearwardly. As such, a user can operate the vehicle using hands and/or feet to control travelling and turning of the vehicle.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: November 22, 2016
    Inventor: Fu-Long Chang
  • Band saw with emergency stop device
    Patent number: 9486933
    Abstract: An emergency stop device for a band saw includes a brake member moveable between a standby position and an active position where the brake member firmly urges and stops a running wheel of the band saw, around which a band saw blade is looped. The brake member is held by a retainer at the standby position when the emergency stop device is inactive. When the emergency stop device is started, the retainer is separated apart from the brake member for enabling the brake member to move by an actuation of a spring member from the standby position to the active position so as to stop the cutting motion of the band saw blade.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: November 8, 2016
    Assignee: OAV EQUIPMENT & TOOLS, INC.
    Inventors: Long-Chang Jan, Hsuan-Chu Liu
  • Configurable clock interface device
    Patent number: 9489007
    Abstract: A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: November 8, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chang-Ting Chen
  • Circuit for voltage detection and protection and operating method thereof
    Patent number: 9490624
    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: November 8, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • METHOD, ELECTRONIC DEVICE AND CONTROLLER FOR RECOVERING ARRAY OF MEMORY CELLS
    Publication number: 20160300616
    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 13, 2016
    Inventors: Kuen-Long Chang, Nai-Ping Kuo, Ken-Hui Chen, Chao-Hsin Lin
  • MEMORY DEVICE AND ERASING METHOD THEREOF
    Publication number: 20160292031
    Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.
    Type: Application
    Filed: June 17, 2016
    Publication date: October 6, 2016
    Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
  • INTEGRATED CIRCUIT AND IMPLEMENTATION METHOD THEREOF
    Publication number: 20160285256
    Abstract: An integrated circuit (IC) including a unit area, a first input/output (IO) cell, a second IO cell, an electrostatic discharge (ESD) component, a first IO pad and a second IO pad is provided. The unit area is divided into several subareas, wherein a subarea of an ith column and a jth row of those subareas is defined as SA(i,j). The first IO cell is arranged in subareas SA(i,j) and SA(i,j+1) of those subareas. The second IO cell is arranged in a subarea SA(i+1,j+1) of those subareas. The ESD component is arranged in at lease one of the subareas of the jth row. The first IO pad is arranged on the first IO cell, and electrically connected to the first IO cell. The second IO pad is arranged on the second IO cell, and electrically connected to the second IO cell.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 29, 2016
    Applicant: Faraday Technology Corp.
    Inventors: Jeng-Huang Wu, Tang-Long Chang, Wang-Chin Chen
  • Circuit with output switch
    Patent number: 9450577
    Abstract: An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 20, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Su-Chueh Lo, Tzu-Ting Chiu
  • Stabilization of output timing delay
    Patent number: 9444462
    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: September 13, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen