Abstract: A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.

Abstract: A system (100) and a method (300) for detecting brake fading in a vehicle. The system (100) includes at least one sensor (140-143) configured to gather data about at least one brake (110-113) in a vehicle (105), a braking system (130), a braking system sensor (145) configured to gather data about the braking system (130), and an electronic controller (150) configured to receive data from at least one selected from the group consisting of the at least one sensor (140-143) and the braking system sensor (145), and determine, based on the data, a level of brake fading of the vehicle (105). The method (300) comprises receiving (305), with an electronic controller (150), data from at least one of the group consisting of at least one sensor (140-143) and a braking system sensor (145); and determining (310), with the electronic controller (150), a level of brake fading of a vehicle (105) based upon the data.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Abstract: A smart voice system is disclosed. The smart voice system includes a data receiving module, a voice message receiving module, a voice response module and a voice message output module. The data receiving module receives a hearing evaluation data of a user, and acquiring a hearing parameter according to the hearing evaluation data. The voice message receiving module receives a voice message inputted by the user. The voice response module acquires a response voice message corresponding to the voice message and the frequency of the response voice message is adjusted according to the hearing parameter. The voice message output module outputs the response voice message.

Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

Abstract: A system and method for generating a pressure-volume curve for a hydraulic system in a vehicle. The system includes a plunger coupled to the hydraulic system, a pressure sensor configured to detect a pressure of the hydraulic system, and an electronic controller configured to access a prior pressure-volume curve from a memory, generate a signal to move the plunger, receive a pressure from the pressure sensor, generate a new pressure-volume curve based upon the received pressure and a position of the plunger, compare the new pressure-volume curve to the prior pressure-volume curve, in response to the new pressure-volume curve and the prior pressure-volume curve differing by at least a threshold value, replace the prior pressure-volume curve with the new pressure-volume curve in the memory, and actuating the hydraulic system based upon the stored pressure-volume curve.

Abstract: A memory device can include a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

Abstract: An adjustable trimming mechanism includes a wheel module having a wheel mount and a wheel disposed on the wheel mount, and a motor module having a motor mount, a slide rail disposed on a side of the motor mount, a motor, a slider disposed on the slide rail and connected with the motor, a pull rod and a positioning member threadedly disposed on the slide rail. One of the motor and wheel mounts is located above the other. An end of the slider is connected with the pull rod so that the slider drives the motor to displace together frontward or backward when being pulled by the pull rod. Therefore, when the positioning member is loosened, the position of the motor is adjustable frontward or backward by the cooperation of the pull rod and the slider and thereby the cutter installed on the motor is adjusted simultaneously.

Abstract: An assistance system includes a resistance detecting unit obtaining a resistance factor, a database storing starting torque values and operating torque values, a torque calculation unit including a controller, and a torque-control handlebar grip operated to trigger an assigned gain and to tune the same to be provided to the torque calculation unit. When switched to an aided mode, the controller calculates a compensated torque value based on one of the starting/operating torque values and the resistance factor, calculates an output torque value by a product of the compensated torque value, the assist ratio and the assigned gain, and controls a torque motor to drive rotation of a driving wheel based on the output torque value.

Abstract: An assistance system includes a resistance detecting unit obtaining a resistance factor, a database storing starting torque values and operating torque values, a torque calculation unit including a controller, and a torque-control handlebar grip operated to trigger an assigned gain and to tune the same to be provided to the torque calculation unit. When switched to an aided mode, the controller calculates a compensated torque value based on one of the starting/operating torque values and the resistance factor, calculates an output torque value by a product of the compensated torque value, the assist ratio and the assigned gain, and controls a torque motor to drive rotation of a driving wheel based on the output torque value.

Abstract: Systems and methods for a steering a vehicle. In one example, a system includes a first wheel, a second wheel, and a skid/differential steering system including an electronic processor. The electronic processor is configured to receive, from an electronic power steering system, a steering failure signal and a target steering angle, determine, based on the target steering angle, a target yaw rate, and drive the first wheel of the vehicle forward and decelerate the second wheel of the vehicle based on the target yaw rate, turning the vehicle.

Abstract: A method for manufacturing a rolled retraction cord is provided. The method comprises the steps of: (A) preparing the sheet, the sheet comprising a first side edge and a second side edge opposite to each other; (B) placing the sheet on a first surface of a first forming member; (C) contacting the first side edge of the sheet with a second surface of a second forming member, the first side edge of the sheet sandwiched between the first surface of the first forming member and the second surface of the second forming member; and (D) applying a force via the first surface or the second surface to the sheet, and rolling the sheet from the first side edge to the second side edge to obtain the retraction cord. With this method, a rolled retraction cord with a smooth surface and enhanced ductility is capable of being provided.

Abstract: A memory device can comprise a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received a command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.