Abstract: A memory device is disclosed in the present invention, comprising a memory array, a logic circuit, a sense amplifier circuit and a read buffer. The logic circuit is configured to perform a read operation in response to a read command and a start address. During the read operation, the logic circuit finds a target data in the memory array. The sense amplifier circuit is configured to read the target data from the memory array during the read operation. The read buffer is configured to temporarily stores and outputs the target data during the read operation. When an interruption event occurs during the read operation, the read buffer preserves a buffer content of the read buffer, and the logic circuit records a read status.

Abstract: A balancing transporter is provided to mitigate occurrence of undesired sudden turning and falling of a user by virtue of various mechanisms that control the source/cause of mistakes and implement post-mistake remedies. Two adjusting members are operated by the user for turning control in a manner that interference between operations on the adjusting members and on handles is prevented. Maximum allowance of difference between wheel speeds is introduced to prevent sudden turns due to inappropriate operation. A rotational interlock unit mechanically enables the adjusting members to rotate in opposite directions to prevent sudden turns. Shock absorption and balance compensation mechanisms are introduced to keep the balancing transporter from tilting.

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

Abstract: The present invention provides a hoof cover that is elastic and stretchable over the hoof of animals such as ruminants and equines. The hoof cover is suitable to be used for the treatment of hoof diseases wherein the cover will securely hold a dressing or a treatment pad. The hoof cover comprises an opening for foot insertion (205) and openings (201, 203) for at least partially exposing the hoof.

Abstract: A frame of a vehicle includes a front fork unit pivotably connected to a head tube of a vehicle body mechanism, a crank axle disposed on the front fork unit for two front-wheel cranks to be pivoted thereon. Two front wheels are pivotably disposed on the cranks, respectively. A front-wheel counteracting mechanism is pivotably connected between each of the cranks and the front fork unit to transmit an impact force to the cranks so as to cause opposite upward and downward movements of the front wheels to thereby keep the front wheels in contact with the ground and to render movement of the vehicle steady and safe.

Abstract: A feeding system with numerically adjustable pneumatic cylinder speeds includes: a frame; an X-axis pneumatic cylinder; a Z-axis pneumatic cylinder; a feeding table connected to the pneumatic cylinders in order to be driven into motion in the X- and Z-axis directions; an X-axis detection module; a Z-axis detection module; a microcomputer; and a display screen electrically connected to the microcomputer. The microcomputer uses each detection module to determine the time interval between the instant at which the piston rod of the corresponding pneumatic cylinder passes the corresponding starting point and a subsequent instant at which the same piston rod passes the corresponding endpoint. The time intervals thus determined are defined as a duration of X-axis forward movement and a duration of Z-axis forward movement respectively. Both durations are displayed on the display screen.

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: Systems and methods for performing a parallel parking maneuver of a host vehicle between a first object and a second object. In one embodiment, the method includes detecting a parking mode and determining a parking space size upon detecting the parking mode. The method also includes selecting a left rear wheel of the host vehicle or a right rear wheel of the host vehicle. The method further includes applying a first braking force, sufficient to lock-up the selected rear wheel of the host vehicle, to the selected rear wheel of the host vehicle when the parking space size is less than a size threshold. The method also includes applying a second braking force to the selected rear wheel of the host vehicle when the parking space size is greater than or equal to the size threshold. The second braking force is less than the first braking force.

Abstract: A memory device includes an error code generator, one or more first pins coupled to an external data bus, and one or more second pins coupled to an external system interface. The one or more first pins output data chunks to the data bus during a period of memory operation; and the error code generator is configured to transmit a status code via the one or more second pins during the period of memory operation. The status code indicates at least one of an error was detected, an error was detected and corrected, or an error was detected and not corrected.

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

Abstract: A sound adjustment method applied to a sound adjustment system is disclosed. The sound adjustment system includes a sound receiving module, a sound identification module, a sound frequency conversion module and a sound equalizer. The sound adjustment method includes the steps of: receiving a sound signal via the sound receiving module; identifying the sound signal via the sound identification module to determine a type of the sound signal; if the sound signal is a voice signal, executing a frequency conversion of the voice signal via the sound frequency conversion module such that the voice signal becomes a frequency-converted voice signal; if the sound signal is a non-voice signal, adjusting the non-voice signal via the sound equalizer such that the non-voice signal becomes an equalizer-adjusted sound signal.

Abstract: An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

Abstract: A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.

Abstract: A method for facilitating handwriting practice includes: generating handwriting strokes in response to user input of user-writing strokes; generating an input image that includes the handwriting strokes, and that has a shape similar to a shape of a standard image associated with a standard word character; scaling the input image to generate a scaled image with a size that is the same as a size the standard image; overlapping the standard image and the scaled image; comparing an nth handwriting stroke in the scaled image with an nth standard stroke in a standard order of the standard word character; and when the nth handwriting stroke does not correspond in position to the nth standard stroke, displaying a notification of a stroke order error.

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Abstract: A memory device is disclosed in the present invention, comprising a memory array, a logic circuit, a sense amplifier circuit and a read buffer. The logic circuit is configured to perform a read operation in response to a read command and a start address. During the read operation, the logic circuit finds a target data in the memory array. The sense amplifier circuit is configured to read the target data from the memory array during the read operation. The read buffer is configured to temporarily stores and outputs the target data during the read operation. When an interruption event occurs during the read operation, the read buffer preserves a buffer content of the read buffer, and the logic circuit records a read status.

Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.