Abstract: Disclosed are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit includes a plurality of transistors, wherein at least one transistor includes an active layer and two gate electrodes. The substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on one side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

Abstract: Aspects of the present disclosure include methods, apparatuses, and computer readable media for determining a connected mode discontinuous reception (C-DRX) short cycle value, transmitting a C-DRX short cycle request to a base station, the C-DRX short cycle request including the C-DRX short cycle value, receiving a first confirmation indicating the base station accepting the C-DRX short cycle value associated with the C-DRX short cycle request, determining an averaging window value based on the C-DRX short cycle value, transmitting an averaging window request to the base station, the averaging window request including the averaging window value, receiving a second confirmation indicating the base station accepting the averaging window value associated with the averaging window request, and communicating with the base station based on the C-DRX short cycle value and the averaging window value.

Abstract: Disclosed is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, the gate drive circuit includes a plurality of cascaded shift register units, and a shift register unit is connected with at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected with a first group of clock signal lines, and the second output circuit is connected with the first group of clock signal lines and a second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit.

Abstract: The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixels. The array substrate includes: a plurality of power lines which are arranged in a conductive layer on a base substrate, are arranged at intervals along a first direction and extend along a second direction, and are used for providing power signals to the sub-pixels; and a plurality of power leads which are arranged in another conductive layer, are arranged at intervals along the second direction and extend along the first direction. Projections of at least one of the power lines and at least one of the power leads on the base substrate intersect, and the projections of the power lines and the power leads on the base substrate form a grid-like structure.

Abstract: Devices and methods for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.

Abstract: A display substrate and a display device. The display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first passage region. Each pixel island includes at least one pixel, each pixel includes a plurality of first driving lines, the first passage region is provided with a plurality of first connection lines, each of the plurality of pixel islands further includes a plurality of transfer lines, and the plurality of transfer lines are arranged in different layers from the plurality of first driving lines and cross each other to form a plurality of overlapping regions; the plurality of transfer lines are electrically connected with the plurality of first driving lines through via holes located in part of the overlapping regions, and the transfer lines in two adjacent pixel islands are respectively connected with the plurality of first connection lines in the first passage region.

Abstract: Disclosed are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit includes a plurality of transistors, wherein at least one transistor includes an active layer and two gate electrodes. The substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on one side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

Abstract: An independent electronic steering axle includes: a swing axle, where the swing axle is rotatably connected to a vehicle body; wheel frames, where the wheel frames are respectively arranged at two ends of the swing axle, an upper part of the wheel frame is rotatably connected to an end of the swing axle through a rotary support member, and a lower part of the wheel frame is mounted with a steering wheel; steering motors, where the steering motors are respectively arranged at the two ends of the swing axle; and feedback assemblies, where the feedback assemblies are respectively arranged at the two ends of the swing axle. The independent electronic steering axle is applied on the four-fulcrum counterbalance forklift, which realizes a steering function of the forklift, provides an accurate steering control progress, greatly improves a steering response speed, and reduces an energy consumption of the forklift and noise.

Abstract: A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

Abstract: A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.

Abstract: An error recovery method for a display system interface includes configuring a physical layer circuit in the display system interface for a high-speed mode of communication, causing the physical layer circuit to transmit display data over a serial bus while the physical layer circuit is configured for the high-speed mode of communication, halting transmission of the display data when an error indication signal transitions to an active state, configuring the physical layer circuit for a low-power mode of communication after terminating the transmission of the display data, reconfiguring the physical layer circuit for the high-speed mode of communication when the error indication signal transitions to an inactive state, and causing the physical layer circuit to resume the transmission of the display data after reconfiguring the physical layer circuit for the high-speed mode of communication.

Abstract: The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixels. The array substrate includes: a plurality of power lines which are arranged in a conductive layer on a base substrate, are arranged at intervals along a first direction and extend along a second direction, and are used for providing power signals to the sub-pixels; and a plurality of power leads which are arranged in another conductive layer, are arranged at intervals along the second direction and extend along the first direction. Projections of at least one of the power lines and at least one of the power leads on the base substrate intersect, and the projections of the power lines and the power leads on the base substrate form a grid-like structure.

Abstract: A display panel and a display device. Because the pixel distribution density in a second display subarea (A12) is lower than that in a first display subarea (A11), the quantities of sub-pixels (pix) connected to scanning lines are not completely the same; a sub-pixel row having the greatest quantity of sub-pixels (pix) in the display panel is taken as a reference sub-pixel row, the quantity of the sub-pixels (pix) of the reference sub-pixel row is taken as a reference value, a sub-pixel row having the quantity of sub-pixels (pix) smaller than the reference value is taken as a compensation sub-pixel row, and a scanning line connected to the compensation sub-pixel row is taken as a first scanning line; the display panel is provided with load compensation units corresponding to at least part of the first scanning lines, and the load compensation units are located in the second display subarea.

Abstract: Methods and apparatuses are provided for alignment of hardware and software Vsync signals through filtering out delayed timestamp signals in a hardware timestamp signal used to generate the software Vsync. The alignment may occur when a display client is operating in a video mode but not a command mode. A compositor or processing unit may receive a hardware Vsync signal from a display using a video mode, generate a hardware timestamp signal based on the hardware Vsync signal, determine a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames, determine whether the delay for the pulse is over a threshold, and control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold. Thus, accurate Vsync signal synchronization may occur.

Abstract: A pixel circuit, a driving method therefor and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a leak-proof sub-circuit, a storage sub-circuit and a light-emitting element. The reset sub-circuit is configured to reset a fourth node under control of a signal of a light-emitting control signal terminal and reset a fifth node under control of a signal of a reset control signal terminal. The compensation sub-circuit is configured to compensate a threshold voltage of the driving sub-circuit to the fifth node under the control of a signal of a first scanning signal terminal. The leak-proof sub-circuit is configured to write a signal of the fifth node into a first node under control of a signal of a second scanning signal terminal.

Abstract: A display substrate has sub-pixels. Each column of sub-pixels includes first and second sub-pixels alternately arranged. The display substrate includes a base, a second source-drain metal layer including first and second connection portions, and a first source-drain metal layer including first and second data lines alternately arranged. A pixel driving circuit of each first sub-pixel is connected to a second end of a first connection portion, and a first end there is connected to a corresponding first data line. A pixel driving circuit of each second sub-pixel is connected to a second end of a second connection portion, and a first end thereof is connected to a corresponding second data line. In a same column of sub-pixels, an extension direction of a first line connecting a second end of a first connection portion and a second end of a second connection portion is substantially parallel to a second direction.

Abstract: The disclosure belongs to a field of hydraulic equipment, and in particular to an anti-rolling damping device for floating wind turbines. The specific technical scheme: low ends of buoys are connected with an upper surface of a support plate through a damping assembly, and the damping assembly includes a piston cylinder fixedly arranged on the support plate, a piston plate is slidably arranged in the piston cylinder, a piston rod is arranged at one end of the piston plate far from the support plate, the piston rod extends out of the piston cylinder and is fixedly connected with the buoys, and a plurality of first through holes are arranged on a side wall of the piston cylinder near the lower part. The buoys sink with waves, and the piston plate slides downwards in the piston cylinder.

Abstract: The disclosure belongs to a field of hydraulic equipment, and in particular to an anti-rolling damping device for floating wind turbines. The specific technical scheme: low ends of buoys are connected with an upper surface of a support plate through a damping assembly, and the damping assembly includes a piston cylinder fixedly arranged on the support plate, a piston plate is slidably arranged in the piston cylinder, a piston rod is arranged at one end of the piston plate far from the support plate, the piston rod extends out of the piston cylinder and is fixedly connected with the buoys, and a plurality of first through holes are arranged on a side wall of the piston cylinder near the lower part. The buoys sink with waves, and the piston plate slides downwards in the piston cylinder.

Abstract: The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a pixel unit, including a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor and a threshold compensation transistor; a first power line configured to supply a first power supply voltage to the pixel circuit; a blocker, electrically connected with the first power line; and a first conductive structure, connected with the gate electrode of the driving transistor, the first channel and the second channel of the threshold compensation transistor are connected by a conductive connection portion; an area of an orthographic projection of a portion of the blocker overlapping with the first conductive structure on the base substrate is larger than an area of an orthographic projection of a portion of the blocker overlapping with the conductive connection portion on the base substrate.